t o r m f o r v e r i f y i n g t h e o p e r a t i o n o f t h e S 3 0 2 8
transceiver interface circuit. This document provides
information on the board contents and layout. It should
be used in conjuction with the S3028 data sheet,
which contains full technical details on the chips
nents and user accessible interface and control points.
On-board isolation buffers and terminations are repre-
sented schematically. The evaluation board can be
configured for operation with either the S3026 Clock
Recovery Unit (CRU) or with buffered access to the
serial data and clock inputs of the S3028. The S3026
in turn can be operated using the on-board 19MCK
output of the S3028 for its TTLREF reference, or an
external reference can be supplied via the S3026
board allowing separate control of voltage levels for
the input signal termination, the S3028 and the S3026,
the S3028 output terminations, and the AC coupled
external test equipment environment or other standard
ECL and/or +5V referenced ECL systems to supply
the correct +5V referenced ECL to the device. The
separately powered output buffers allow easy connec-
tion to the 50
standard ECL I/O of serial Bit Error Rate Testers
(BERT) and jitter analyzers. Table 1 illustrates the
nominal input voltages for DUT Vcc and O/P VTT. The
options for BUF VEE and BUF VCC are paired
ferent serial data input/output signals and output clock.
Additional SMA connectors are provided for an
optional differential serial input clock, the external TTL
reference clock and the optional External Parallel
Input Clock (EXT PICLK). See Figure 1 for locations.
AC coupled PECL inputs. Jumper options connect the
buffered signal to the on-board S3026 where the serial
clock is recovered from the transitions on these inputs.
These inputs can also be directly connected to the
RSDP/N inputs of the S3028 via alternate jumper
options. In this mode the RSCLKP/N inputs must be
provided with a correctly aligned serial clock. On-
board termination of 330
ential AC coupled PECL inputs. These inputs are not
used if the S3026 is serving as the clock recovery
device. As stated above, jumper options connect the
buffered output directly to the RSCLKP/N inputs of the
S3028 if the S3026 is not used.
PECL outputs. The serial output data stream from the
transmitter section of the S3028. The buffered outputs
can drive PECL, ECL, or ground terminated instru-
ment inputs. Driven inputs must provide a 50
PECL outputs. The transmit serial clock that can be
used to re-time the TSDP/N signal. The buffered out-
puts can drive PECL, ECL, or ground terminated
instrument inputs. Driven inputs must provide a 50
selectable source jumper for the parallel input clock to
the transmitter section. Used when an external data
source is driving the PIN[7:0] parallel data inputs.
input. Selectable source jumper for the reference clock
of the S3026 Clock Recovery Unit (CRU). Jumpers
select between this input and the 19MCK reference
provided by the S3028.
AC coupled PECL inputs. These inputs must be pro-
vided with a differential ECL/PECL clock of 19.44,
38.88, 51.84, or 77.76 MHz as selected by the REF-
SEL[1:0] switches of the 12 section DIP switch.
S3028 transceiver are available at a 4 x 9 pin header
array at the right edge of the evaluation board. Figure
1 identifies the two columns of signal pairs. Ground pin
columns are also provided to allow connection with
0.1" grid shielded ribbon cable to parallel data sources
and data analyzers.
lel data output (POUT[7:0]) and the parallel word clock
output (POCLK) to be directly connected to the trans-
mitter parallel data inputs (PIN[7:0]) and the parallel
input clock (PICLK). In this mode, the POCLK should
be connected to the REFCLKN input via the on-board
jumper, and when the S3026 is installed, the S3026
EXT CLK must be used for the S3026 reference. Note:
The board must be supplied with an external reference
via REFCLKP/N, S3026 EXT CLK or RSCLKP/N for
tional signals. The four signals are identified in Figure
output reference from the transmitter PLL. This output
is used to coordinate byte-wide transfers via the paral-
lel data bus.
the SONET/SDH framing pattern.
the transmitter PLL is properly locked to the reference
output derived from the S3028 PLL available at the
header pin for monitoring, and jumper connectable
internally for use as a reference by the S3026. Note:
This reference mode is not recommended when oper-
ating in the parallel loopback mode.
19MCK pins to allow shielded or twisted pair connec-
tion to these clocking signals.
arrays, one four station array and one twelve station
array, to control the static control functions of the on-
board devices. For both arrays, the OFF (open) condi-
tion of the DIP switch asserts a logic low on the
assigned signal, and the ON condition asserts a logic
inputs of the S3026. The SDN switch, when OFF
allows the S3026 to recover the clock from the serial
data stream. ON will force the S3026 to lock to the ref-
to the reference clock. This switch should be ON for
clock recovery operation.
622.08 Mbit/s. OFF selects 155.52 Mbit/s.
modes of the S3028. Please note that it is generally
advisable to operate the S3028 and the S3026 in simi-
lar or at least compatible modes. If the POCLK from
the receiver is being used as the reference clock for
the transmitter, the REFSEL[1:0] switches must be set
to the same frequency as the word rate determined by
the BUSWIDTH and MODE switches for the S3028
and the MODE switch for the S3026.
switch controls the master reset of the S3028.
specific control functions.
notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the
information being relied on is current.
does it convey any license under its patent rights nor the rights of others.
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