HTML datasheet archive (search documentation on electronic components) Search datasheet (1.687.043 components)
Search field

Datasheet: EV3023 (Applied Micro Circuits Corp.)

Sonet/sdh/atm Oc-12 Clock and Data Recovery Evaluation Board

 

Download: PDF   ZIP
 
1
EV3023
SONET/SDH/ATM OC-12 CLOCK AND DATA RECOVERY EVALUATION BOARD
November 19, 1999
EV3023
SONET/SDH/ATM OC-12 CLOCK AND DATA RECOVERY EVALUATION BOARD
DESCRIPTION
The S3023 evaluation board provides a flexible platform for verifying the operation of the S3023 clock and data
recovery interface circuit. This document provides information on the board contents. It should be used in
conjunction with the S3023 data sheet, which contains full technical details on the chips operation.
Figure 1 shows the outline of the S3023 evaluation board. Figure 2 shows the block diagram of how the S3023
evaluation board should be connected to test equipment for Bit Error Rate (BER) testing.
Figure 1. S3023 Evaluation Board Top View
SERDATIN
SERDATIP
GND
GND
DUT
VEE
"1"
"0"
AMCC
6290 SEQUENCE DR.
SAN DIEGO, CA 92121
APPLIED MICRO CIRCUITS CORPORATION
S3023 SONET/SDH/ATM OC-3/12 CRU
TTLREF
GND
EXT. VEE(OSC)
DUT VEE
LVTTL XTAL
OSCLLATOR
GND
BYPASS
SDN
LCKREFN
MODE
GND
TO DUT
FROM DIPSW
1
2
3
SERDATOP
SERDATON
SERCLKOP
SERCLKON
NOTE 1
GND
LOCKDET
DUT
VCC
Tied together for formal
operation of LVTTL osc.
S3023
Note 1. Demo board is set up for a crystal oscillator with a "0"
jumper between 2 and 3. When TTLREF is to be used, a "0"
jumper should be placed between 1 to 2, and the jumper between 2 and 3 should be removed.
2
EV3023
SONET/SDH/ATM OC-12 CLOCK AND DATA RECOVERY EVALUATION BOARD
November 19, 1999
Figure 2 depicts how the S3023 evaluation board can be connected for BER or jitter measurements, and shows all
of the DIP switch settings. In addition, it shows the low voltage ECL (LVECL) power supply requirements for use
with test equipment that utilizes 50
to (-2V) input termination. In this configuration the S3023 is configured for use
with the internal S3023 Clock Recovery Unit (CRU), using a 19.44 MHz reference and operating at STS-12.
Figure 2. S3023 BER Test Setup
(for jitter)
BERT RX
TEKTRONIX GIGABERT 700 or
EQUIVALENT
S3023 BER
TEST
DATA_P
DATA_N
DATA_IN
SINGLE ENDED INPUT TO
DIFFERENTIAL OUTPUT BUFFER
S3023
SERDATIP
SERDATIN
SERDATOP
SERDATON
SERCLKOP
SERCLKON
DATA/IN_P
DATA/IN_N
CLK/IN_P
CLK/IN_N
BERT TX
TEKTRONIX GIGABERT 700 or
EQUIVALENT
CLK/OUT_P
CLK/OUT_N
DATA/OUT_P
DATA/OUT_N
THRU_DATA
REF_CLK
DATA_OUT
CLK_IN
CLK_OUT
TEKTRONIX
SJ 300
(for BER)
POWER SUPPLY
GND = 0V
DUTVCC = 0V
DUTVEE = -3.3V
BYPASS = "0"
SDN = "1"
LCKREFN = "1"
MODE = "1"
-3.3V
(INPUT TERMINATION SET TO (-2V))
DUTVCC
DUTVEE
3
EV3023
SONET/SDH/ATM OC-12 CLOCK AND DATA RECOVERY EVALUATION BOARD
November 19, 1999
ELECTRICAL CONNECTIONS
Power Connections
Terminal posts are provided at the top edge of the board for VCC and VEE. The S3023 evaluation board can be
configured with ECL, PECL and level shifted (LSECL) I/O so that the board can be configured to operate with
different types of standard test equipment. Figures 3 through 5 demonstrate the different types of input and
output waveforms that the S3023 evaluation board can output with the different voltage settings of VCC and VEE
per Table 1. Note that the TTL I/O's voltage level will change to non-standard levels when the S3023 evaluation
board is powered in the LSECL or LVECL power supply modes.
The external test equipment environment or other standard ECL and/or +3.3V referenced ECL systems can
interface to the S3023 evaluation board. The board as shown by Figures 1 and 2 can be powered to allow easy
connection to the 50
to (-2V) standard ECL I/O of serial Bit Error Rate Testers (BERT) and jitter analyzers
(Note: not all test equipment is 50
to (-2V) termination compatible). Table 1 illustrates the nominal input
voltages for DUT VCC and VEE voltage levels shown in Figures 3 through 5. Figures 3 and 4 show that the
voltages track with VEE, and Figure 5 show that the voltages track with VCC.
SMA Connectors
SMA connectors are provided for the differential serial data input/output signals and output clock. The additional
SMA connector provides for an optional TTL reference clock.
Receive Serial Data [SERDATIP/N] -- Differential LVPECL inputs. Serial data inputs of the S3023.
Serial Data Output [SERDATOP/N] -- Differential LVPECL outputs. Serial data outputs of the S3023.
Serial Clock Output [SERCLKOP/N] -- Differential LVPECL outputs. Serial recovered clock output of the
S3023
TTL Reference Clock [TTLREF] -- LVTTL input. These inputs must be provided with a 19.44 MHz LVTTL
crystal oscillator.
DIP SWITCHES
The evaluation board is equipped with a DIP switch, to control the static control functions of the on-board device.
The OFF (open = "0") condition of the DIP switch asserts a logic low on the assigned signal, and the ON (closed
= "1") condition asserts a logic high. Figure 2 shows the particular DIP switch settings that are needed for a
particular test case.
Table 1. Power Connections for DUT and Test Equipment Interface
y
l
p
p
u
S
r
e
w
o
P
e
g
a
t
l
o
V
t
u
p
n
I
l
a
n
i
m
o
N
l
a
n
g
i
S
f
o
e
p
y
T
n
o
i
t
a
n
i
m
r
e
T
t
u
p
t
u
O
L
C
E
C
C
V
T
U
D
E
E
V
T
U
D
V
3
.
3
+
V
0
L
C
E
P
V
L
0
5
V
2
-
C
C
V
o
t
C
C
V
T
U
D
E
E
V
T
U
D
V
0
V
3
.
3
-
L
C
E
V
L
0
5
V
2
-
o
t
C
C
V
T
U
D
E
E
V
T
U
D
V
2
+
V
3
.
1
-
L
C
E
S
L
0
5
D
N
G
o
t
4
EV3023
SONET/SDH/ATM OC-12 CLOCK AND DATA RECOVERY EVALUATION BOARD
November 19, 1999
Figure 3. LVECL Signal Waveform
Figure 4. LSECL Signal Waveform
Figure 5. LVPECL Signal Waveform
VCC = 0V
-0.8V
-1.3V
-1.8V
Termination = 50
to -2V
VEE = -3.3V +/- 5%
LVECL
Termination = 50
to GND
LSECL
VCC = +2V
+1.2V
+0.7V
+0.2V
VEE = -1.3V +/- 5%
LVPECL
VCC = +3.3V +/- 5%
2.5V
2V
1.5V
VEE = 0V
Termination = 50
to (VCC -2V)
5
EV3023
SONET/SDH/ATM OC-12 CLOCK AND DATA RECOVERY EVALUATION BOARD
November 19, 1999
Figure 6. S3023 Evaluation Board Schematic
C5
VEE
GND
LOCKDET
R8
VEE
C2
C1
JP1
C2
C1
JP3
R1
VCC
J2
J7
C4
C3
GND
4
VCC
3
OUTP
2
VEE
1
NC
XT
ALOSC
U2
R3
R2
VCC
LOCKDET
MODE
LCKREFN
VEE
MODE
LCKREFN
SDN
BYPASS
R4
R5
S3023
U1
A
VCC
SERDA
TIP
SERDA
TIN
AGND
LOCKDET
MODE
TTLREF
LCKREFN
DGND
DVCC
SERCLKON
SERCLKOP
SERDA
T
O
N
SERDA
T
O
P
SDN
BYP
ASS
CAP2
CAP1
AGND
A
VCC
1
2
3
4
5
6
7
8
9
10
1
1
12
13
14
15
16
17
18
19
20
C6
VCC
1k
U4
5
4
3
2
1
U6
4pswitch
U3
1
3
5
7
2
4
6
8
J8
2
3
4
1
A
VCC2
A
VCC1
J1
VEE
VCC
L1
L2
C1
C2
VEE
VEE
C16
C17
C19
R6
R7
C7
C18
C2
C1
JP2
SDN
BYP
ASS
GND
10k
U5
5
4
3
2
1
VEE
C8
C9
C10
C14
C15
C11
C12
C13
J4
J3
J6
J5
A
VCC1
A
VCC2
© 2018 • ICSheet
Contact form
Main page