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Datasheet: 5962F9563801QQC (Aeroflex Circuit Technology)

Radiation-Hardened MicroController

 

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Aeroflex Circuit Technology
- 1
Standard Products
UT69RH051 Radiation-Hardened MicroController
Data Sheet
June 2004
FEATURES
Three 16-bit timer/counters
- High speed output
- Compare/capture
- Pulse width modulator
- Watchdog timer capabilities
256 bytes of on-chip data RAM
32 programmable I/O lines
7 interrupt sources
Programmable serial channel with:
- Framing error detection
- Automatic address recognition
TTL and CMOS compatible logic levels
64K external data and program memory space
MCS-51 fully compatible instruction set
Flexible clock operation
- 1Hz to 20MHz with external clock
- 2MHz to 20MHz using internal oscillator with external
crystal
Radiation-hardened process and design; total dose irradia-
tion testing MIL-STD-883 Method 1019
- Total dose: 1.0E6 rads(Si)
- Latchup immune
Packaging options:
- 40-pin 100-mil center DIP (0.600 x 2.00)
- 44-lead 25-mil center Flatpack (0.670 x 0.800)
Standard Microcircuit Drawing 5962-95638 available
- QML Q & V compliant
RAM
PORT 0
LATCH
PORT 2
LATCH
PORT 0
DRIVERS
PORT 2
DRIVERS
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCREMENTER
PROGRAM
COUNTER
DPTR
PORT 3
LATCH
PORT 3
DRIVERS
PORT 1
DRIVERS
OSC.
PORT 1
LATCH
PSW
TMP3
B
REGISTER
ACC
STACK
POINTER
ALU
TMP2
TMP1
SPECIAL FUNCTION
REGISTERS,
TIMERS,
PCA,
SERIAL PORT
MICR
O-
RAM A
DDRESS
RE
GISTER
SEQUENCER
INST
RUCT
ION
REGISTER
PSEN
ALE
EA
RST
P1.0 - P1.7
P3.0 - P3.7
XTAL2
XTAL1
Figure 1. UT69RH051 MicroController Block Diagram
2
1.0 INTRODUCTION
The UT69RH051 is a radiation-tolerant 8-bit microcontroller
that is pin equivalent to the MCS-51 industry standard
microcontroller when in a 40-pin DIP. The UT69RH051's static
design allows operation from 1Hz to 20MHz. This data sheet
describes hardware and software interfaces to the UT69RH051.
2.0 SIGNAL DESCRIPTION
V
DD
: +5V Supply voltage
V
SS
: Circuit Ground
Port 0 (P0.0 - P0.7): Port 0 is an 8-bit port. Port 0 pins are used
as the low-order multiplexed address and data bus during
accesses to external program and data memory. Port 0 pins use
internal pullups when emitting 1's and are TTL compatible.
Port 1 (P1.0 - P1.7): Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The output buffers can drive TTL loads. When
the Port 1 pins have 1's written to them, they are pulled high by
the internal pullups and can be used as inputs in this state. As
inputs, any pins that are externally pulled low sources current
because of the pullups. In addition, Port 1 pins have the alternate
uses shown in table 1.
Port 2 (P2.0 - P2.7): Port 2 is an 8-bit port. Port 2 pins are used
as the high-order address bus during accesses to external Program
Memory and during accesses to external Data Memory that uses
16-bit addresses (i.e., MOVX@DPTR). Port 2 uses internal
pullups when emitting 1's in this mode. During operations that
do not require a 16-bit address, Port 2 emits the contents of the
P2 Special Function Registers (SFR). The pins have internal
pullups and drives TTL loads.
Port 3 (P3.0 - P3.7): Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The output buffers can drive TTL loads. When
the Port 3 pins have 1's written to them, they are pulled high by
the internal pullups and can be used as inputs in this state. As
inputs, any pins that are externally pulled low sources current
because of the pullups. In addition, Port 3 pins have the alternate
uses shown in table 2.
Table 1. Port 1 Alternate Functions
Table 2. Port 3 Alternate Functions
Port
Pin
Alternate
Name
Alternate Function
P1.0
T2
External clock input to Timer/
Counter 2
P1.1
T2EX
Timer/Counter 2 Capture/Reload
trigger and direction control
P1.2
ECI
External count input to PCA
P1.3
CEX0
External I/O for PCA capture/
compare Module 0
P1.4
CEX1
External I/O for PCA capture/
compare Module 1
P1.5
CEX2
External I/O for PCA capture/
compare Module 2
P1.6
CEX3
External I/O for PCA capture/
compare Module 3
P1.7
CEX4
External I/O for PCA capture/
compare Module 4
Port
Pin
Alternate
Name
Alternate Function
P3.0
RXD
Serial port input
P3.1
TXD
Serial port output
P3.2
INT0
External interrupt 0
P3.3
INT1
External interrupt 1
P3.4
T0
External clock input for Timer 0
P3.5
T1
External clock input for Timer 1
P3.6
WR
External Data Memory write
strobe
P3.7
RD
External Data Memory read strobe
3
RST: Reset Input. A high on this input for 24 oscillator periods
while the oscillator is running resets the device. All ports and
SFRs reset to their default conditions. Internal data memory is
undefined after reset. Program execution begins within 12
oscillator periods (one machine cycle) after the RST signal is
brought low. RST contains an internal pulldown resistor to allow
implementing power-up reset with only an external capacitor.
ALE: Address Latch Enable. The ALE output is a pulse for
latching the low byte of the address during accesses to external
memory. In normal operation, the ALE pulse is output every sixth
oscillator cycle and may be used for external timing or clocking.
However, during each access to external Data Memory (MOVX
instruction), one ALE pulse is skipped.
PSEN: Program Store Enable. This active low signal is the read
strobe to the external program memory. PSEN activates every
sixth oscillator cycle except that two PSEN activations are
skipped during external data memory accesses.
EA: External Access Enable. This pin should be strapped to V
SS
(Ground) for the UT69RH051.
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
2.1 Hardware/Software Interface
2.1.1 Memory
The UT69RH051 has a separate address space for Program and
Data Memory. Internally, the UT69RH051 contains 256 bytes
of Data Memory. It addresses up to 64Kbytes of external Data
Memory and 64Kbytes of external Program Memory.
2.1.1.1 Program Memory
There is no internal program memory in the UT69RH051. All
program memory is accessed as external through ports P0 and
P2. The EA pin must be tied to V
SS
(ground) to enable access to
external locations 0000
H
through 7FFF
H
. Following reset, the
UT69RH051 fetches the first instruction at address 0000h.
2.1.1.2 Data Memory
The UT69RH051 implements 256 bytes of internal data RAM.
The upper 128 bytes of this RAM occupy a parallel address space
to the SFRs. The CPU determines if the internal access to an
address above 7F
H
is to the upper 128 bytes of RAM or to the
SFR space by the addressing mode of the instruction. If direct
addressing is used, the access is to the SFR space. If indirect
addressing is used, the access is to the internal RAM. Stack
operations are indirectly addressed so the upper portion of RAM
can be used as stack space. Figure 3 shows the organization of
the internal Data Memory.
The first 32 bytes are reserved for four register banks of eight
bytes each. The processor uses one of the four banks as its
working registers depending on the RS1 and RS0 bits in the PSW
SFR. At reset, bank 0 is selected. If four register banks are not
required, use the unused banks as general purpose scratch pad
memory. The next 16 bytes (128 bits) are individually bit
addressable. The remaining bytes are byte addressable and can
be used as general purpose scratch pad memory. For addresses
0 - 7F
H
, use either direct or indirect addressing. For addresses
larger than 7F
H
, use only indirect addressing.
In addition to the internal Data Memory, the processor can access
64Kbytes of external Data Memory. The MOVX instruction
accesses external Data Memory.
2.1.2 Special Function Registers
Table 3 contains the SFR memory map. Unoccupied addresses
are not implemented on the device. Read accesses to these
addresses will return unknown values and write accesses will
have no effect.
4
(T2)
P1.0
(T2EX)
P1.1
(ECI)
P1.2
(CEX0)
P1.3
(CEX1)
P1.4
(CEX2)
P1.5
(CEX3)
P1.6
(CEX4)
P1.7
RST
(RXD)
P3.0
(TXD)
P3.1
(INT0)
P3.2
(INT1)
P3.3
(T0)
P3.4
(T1)
P3.5
(WR)
P3.6
(RD)
P3.7
XTAL2
XTAL1
V
SS
V
DD
P0.0
(AD0)
P0.1
(AD1)
P0.2
(AD2)
P0.3
(AD3)
P0.4
(AD4)
P0.5
(AD5)
P0.6
(AD6)
P0.7
(AD7)
EA
ALE
PSEN
P2.7
(A15)
P2.6
(A14)
P2.5
(A13)
P2.4
(A12)
P2.3
(A11)
P2.2
(A10)
P2.1
(A9)
P2.0
(A8)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
17
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
23
24
22
21
V
SS
(T2)
P1.0
(T2EX)
P1.1
NC
(ECI)
P1.2
(CEX0)
P1.3
(CEX1)
P1.4
(CEX2)
P1.5
(CEX3)
P1.6
(CEX4)
P1.7
RST
(RXD)
P3.0
(TXD)
P3.1
(INTO)
P3.2
(INT1)
P3.3
(TO)
P3.4
(T1)
P3.5
(WR)
P3.6
(RD)
P3.7
XTAL2
P0.0
(AD0)
P0.1
(AD1)
P0.2
(AD2)
P0.3
(AD3)
P0.4
(AD4)
P0.5
(AD5)
P0.6
(AD6)
P0.7
(AD7)
EA
ALE
PSEN
P2.7
(A15)
P2.6
(A14)
P2.5
(A13)
P2.4
(A12)
P2.3
(A11)
P2.2
(A10)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
17
19
20
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
27
28
26
25
21
22
24
23
XTAL1
V
SS
V
DD
P2.1
(A9)
P2.0
(A8)
NC
V
DD
Figure 2a. UT69RH051 40-Pin DIP Connections
Figure 2b. UT69RH051 44-Pin Flatpack Connections
5
Figure 3. Internal Data Memory Organization
2.1.3 Reset
The reset input is the RST pin. To reset, hold the RST pin high
for a minimum of 24 oscillator periods while the oscillator is
running. The CPU generates an internal reset from the external
signal. The port pins are driven to the reset state as soon as a valid
high is detected on the RST pin.
While RST is high, PSEN and the port pins are pulled high; ALE
is pulled low. All SFRs are reset to their reset values as shown
in table 3. The internal Data Memory content is indeterminate.
The processor will begin operation one machine cycle after the
RST line is brought low. A memory access occurs immediately
after the RST line is brought low, but the data is not brought into
the processor. The memory access repeats on the next machine
cycle and actual processing begins at that time.
F8
F0
88
80
78
70
38
30
28
20
18
10
08
00
FF
F7
8F
87
7F
77
3F
37
2F
27
1F
17
0F
07
INDIRECT
ACCESS
ONLY
DIRECT OR
INDIRECT
ACCESS
SCRATCH
PAD AREA
BIT
ADDRESSABLE
SEGMENT
REGISTER
BANKS
8 BYTES
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