reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
90 dB S/(N+D)
1 MHz Full Power Bandwidth
On-Chip Sample & Hold Function
Serial Twos Complement Output Format
Low Input Capacitancetyp 50 pF
AGND Sense for Improved Noise Immunity
which uses a switched capacitor/charge redistribution architecture
to achieve a 100 kSPS conversion rate (10
internal nonlinearities through on-chip autocalibration.
chips, a digital control chip fabricated with Analog Devices'
DSP CMOS process and an analog ADC chip fabricated with
the BiMOS II process. Both chips are contained in a single
sample command signal. The output data rate may be as high
as 2.08 MHz, and is controlled by the external clock. The twos
complement format of the output data is MSB first and is di-
rectly compatible with the NPC SM5805 digital decimation fil-
ter used in consumer audio products. The AD1876 is also
compatible with a variety of DSP processors.
and operates from +5 V and
quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
ity levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
Analog Inputs, V
functional operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1876 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Frequency" of a converter is that input frequency which is one-
half the sampling frequency of the converter.
rms sum of the first nineteen harmonic components to the rms
value of a 1 kHz full-scale sine wave input signal and is ex-
pressed in percent (%) or decibels (dB). For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
tio of the rms value of the measured input signal to the rms sum
of all other spectral components below the Nyquist frequency,
including harmonics but excluding dc.
signal at a signal amplitude of 60 dB. In this case, an A-weight
filter is used. The value specified for D-range performance is the
ratio measured plus 60 dB.
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
which m or n is not equal to zero. For example, the second or-
der terms are (f
sured input signals to the rms sum of the distortion terms. The
two signals applied to the converter are of equal amplitude, and
the peak value of their sum is 0.05 dB from full scale. The
IMD products are normalized to a 0 dB input signal.
LOW for the internal sample-hold of the AD1876 to open, thus
holding the value of V
ing calibration, SAMPLE is active HIGH, forcing D
also used to derive D
DI = Digital Input.
DO = Digital Output.
P = Power.
trol over the actual calibration process, normal conversion tim-
ing may also be used for calibration. In this case, however, the
end of calibration.
conversion to clear the internal circuitry of the AD1876 in order
to guarantee subsequent conversion accuracy.
only upon power-up, in which case care should be taken that the
power supplies and voltage reference have stabilized first.
as shown in Figure 2. It is assumed that the part has been cali-
brated and the digital I/O pins have the levels shown at the start
of the timing diagram.
clock pulses which are required to run the 16-bit internal suc-
cessive approximation routine. The analog input is acquired by
taking the SAMPLE line HIGH for a minimum acquisition time
taken to ensure that this negative edge is well defined and jitter
free to reduce the uncertainty (noise) in ac signal acquisition.
On that edge the AD1876 commits itself to the initiated conver-
sion--the input at V
conversion is completed (i.e., BUSY goes LOW). After a delay
of at least t
and reset after the 17th. Both the D
pulses. As indicated in the timing diagram, the 2s complement
output data is presented MSB first. This data may be captured
with the rising edge of D
BUSY goes LOW, and so an acquisition may be initiated even
during the HIGH time of the 17th CLK pulse for maximum
throughput rate while enabling full settling of the sample/hold
circuitry. Note that if SAMPLE is already HIGH when BUSY
goes LOW, then an acquisition is immediately initiated and t
with the logic inputs to avoid digital feedthrough noise. It is not
recommended that CLK be running during V
at the instant of disconnecting V
decision is latched on the positive edge of each valid CLK). For
the same reason, it is also not recommended that the SAMPLE
pin change state during conversion (i.e., until after BUSY re-
The AD1876 is a 16-bit analog-to-digital converter including a
sample/hold input circuit, successive approximation register,
ground sensing circuitry, serial output port and a micro-
controller based autocalibration circuit. These functions are seg-
mented onto two monolithic chips, an analog signal processor
and a digital controller. Both chips are contained within the
determine the value of the analog input voltage. However, in-
stead of the traditional laser-trimmed resistor-ladder approach,
the AD1876 uses a capacitor-array, charge-redistribution tech-
nique. An array of binary-weighted capacitors subdivides the
input value to perform the actual analog to digital conversion.
This capacitor array also serves a sample/hold function without
the need for additional external circuitry.
microcontroller and calibration DAC to measure and compen-
sate capacitor mismatch errors. As each error is determined, its
value is stored in on-chip memory (RAM). Subsequent conver-
sions use these RAM values to improve conversion accuracy.
The autocalibration routine may be invoked at any time. Auto-
calibration insures high performance while eliminating the need
for any user adjustments, and is described in detail below.
the AD1876. These include the actual successive approximation
routine, the autocalibration routine, the sample/hold operation,
and the serial data transmission.
user trims or adjustments. This is accomplished through the use
of on-chip autocalibration.
internally connecting the input circuit to the ground sense cir-
cuit. The resulting offset voltage is measured and stored in
RAM for later use. Next, the capacitor representing the most
significant bit (MSB) is charged to the reference voltage. This
charge is then inverted and shared between the MSB capacitor
and one of equal size composed of all the least significant bits.
The difference in the summation of the charges in each of the
equally sized capacitors represents the amount of capacitor mis-
match. A calibration D/A converter (DAC) adds an appropriate
value of error correction voltage to cancel the mismatch. This
correction factor is also stored in RAM. This process is repeated
for each of the capacitors representing the remaining bits. The
accumulated values in RAM are then used during subsequent
conversions to adjust conversion results.
internal circuitry is reset, the BUSY pin is driven HIGH and the
part prepares for calibration. This is a `hard' reset and will inter-
rupt any conversion or calibration currently in progress. In order
to guarantee that all internal undefined states are cleared, the
CAL pin should he held HIGH for at least 4 CLK cycles. Ac-
tual calibration begins when the CAL pin is taken LOW and
completes in less than 5000 clock cycles or about 2.5 msec with
a continuous 500 nsec clock.
tion. If it is held LOW, D
sampled, stored on internal capacitors and used to correct for
their corresponding errors when needed. Because these voltages
are stored on capacitors, they are subject to leakage decay and
so require refreshing. For this reason the part is required to be
run continuously--i.e., there is a minimum t
conversion is completed. The twos complement output data is
presented MSB first, with MSB data valid on the rising edge of
the second D
AD1876 is to connect one or more AD1876s to an NPC
SM5805 digital filter. This device supplies all signals required to
operate the AD1876 at a 96 kHz sample rate, which is 2
section of this data sheet, accompanied by Figures 9 and 10.
AD1876 including the ADC and SHA. V
cluding the serial output port and the autocalibration controller.
These capacitors should be placed as close as possible to the
package pins as well as the ground connections. The logic sup-
length between the capacitor leads and the respective converter
power supply and common pins. The recommended decoupling
scheme is illustrated in Figure 3.
power supplies can produce undesired changes in the perfor-
mance of the circuit. Analog Devices recommends that well
regulated power supplies with less than 1% ripple be incorpo-
rated into the design of any system using these devices.
attention to board layout. Trace impedance is a significant issue.
A 1.22 mA current through a 0.5
full-scale span. In addition to ground drops, inductive and ca-
pacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital sig-
nals. Finally, power supplies need to be decoupled in order to
filter ac noise.
path. Each signal should have an appropriate analog or digital
return routed close to it. Using this approach, signal loops en-
close a small area, minimizing the inductive coupling of noise.
Wide PC tracks, large gauge wire, and ground planes are highly
recommended to provide low impedance signal paths. Separate
analog and digital ground planes are also desirable, with a single
interconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them, if at all, only at right angles. A solid analog
ground plane around the AD1876 will isolate large switching
ground currents. For these reasons, the use of wire wrap circuit
construction is not recommended; careful printed circuit con-
struction is preferred.
GROUND (AGND), DIGITAL GROUND (DGND) and
ANALOG GROUND SENSE (AGND SENSE). The analog
ground pin is the "high quality" ground reference point for the
device. The analog ground pin should be connected to the ana-
log common point in the system.
ground reference point. This allows for slight differences in level
between the analog ground point in the system and the input
signal ground point. However, no more than 100 mV is recom-
mended between the analog ground pin and the analog ground
sense pin for specified performance.
signals that operate the AD1876. This pin should be connected
to the digital common point in the system. As illustrated in Fig-
ure 3, the analog and digital grounds should be connected to-
gether at one point in the system.
The input voltage range is determined by the value of the refer-
ence voltage; in general, a reference voltage of n volts produces
an input range of
specified with a 5.0 V reference and an analog input of
LSB size (which results from increasing the reference voltage)
will increase the effective S/(N+D) performance for input values
below the point where input distortion occurs. Figure 11 illus-
trates S/(N+D) as a function of input amplitude and reference
AD1876 presents a dynamically changing current load at the
voltage reference as the successive-approximation algorithm
cycles through various choices of capacitor weighting. The out-
put impedance of the reference circuitry must be low so that the
output voltage will remain sufficiently constant as the current
drive changes. In most applications, this requires that the output
of the voltage reference be buffered by an amplifier with low im-
pedance at relatively high frequencies. A (10
tively narrow temperature range, with low cost being important.
Figure 4 shows one such approach towards attaining these goals.
A voltage reference, consisting of a Zener diode, capacitor, resis-
tor and op amp with typical component values, is shown. This
simple circuit has the advantage of low cost, but the reference
voltage value is sensitive to changes in the +12 V supply. Addi-
tionally, changes in the Zener value due to temperature varia-
tions will also be reflected in the reference voltage. R
more current than the op amp can supply.
over temperature and static accuracy are important. Figure 5
shows a voltage reference circuit featuring the 5 V AD586. The
AD586 is a low cost reference which utilizes a buried Zener ar-
chitecture to provide low noise and drift. Over the 0
improved drift, low noise, and excellent initial accuracy. The
AD588 uses a proprietary ion-implanted buried Zener diode in
conjunction with laser-trimmed thin-film resistors for low offset
and gain. The AD588 output is accurate to 0.65 mV from its
value at +25
7. The 1
optimum performance of the AD1876.
input signal. If AGND SENSE is not used, it should be con-
nected to the AGND pin at the package. The AGND SENSE
pin is intended to be tied to potentials within 100 mV of AGND
to maintain specified performance.
each analog input is connected to an internal, discharged 50 pF
capacitor which then charges to the voltage present at the
is taken LOW and the stored charge is used in the subsequent
A/D conversion. In order to limit the demands placed on the
external source by this high initial charging current, an internal
buffer amplifier is employed between the input and this capaci-
tance for a few hundred nanoseconds. During this time the
input pin exhibits typically 20 k
settle, after which SAMPLE is taken LOW. During this time
the input sees only a 50 pF capacitor. Once the sample is taken,
the input is internally floated so that the external input source
sees a very high input resistance and a parasitic input capaci-
tance of typically only 2 pF. As a result, the only dominant input
characteristic which must be considered is the high current steps
which occur when the internal buffers are switched in and out.
AD1876. For ac applications where low cost and low distortion
are desired, the AD711 may be used as shown in Figure 7. An-
other option is the 5532/5534 series. Care should always be
taken with op amp selection--many available op amps do not
meet the necessary low distortion requirements with even mod-
erate loading conditions.
tester to verify the electrical performance of every AD1876. The
test system consists of two main sections, an input signal gen-
erator and a digital data and control section.
noise-free, band limited tone to the input of the device. This in-
put frequency is 1.06 kHz. The test tone is passed through a
bandpass filter to remove distortion products and then buffered
by a high performance op amp. An external 5.000 V reference
voltage is also supplied by this section.
clock and the control signals for calibration, conversion and data
transmission. This section of the tester also contains the pro-
cessing unit that calculates the actual performance of the device
device is calibrated by its on-board controller. Next, the device
under test digitizes the input waveform. This conversion is
performed at a 96 kSPS rate and transmits the resulting serial
data to the tester. The tester performs an FFT on the test data
and determines the actual performance of the device.
of the AD1876 is measured. AC parameters, which include
S/(N+D), THD, etc., reflect the AD1876's effect on the spec-
tral content of the analog input signal. Figures 11 through 15
provide information on the AD1876's ac performance under a
variety of conditions.
reduces the effects of noise and, therefore, improves such pa-
rameters as S/(N+D) and THD. AD1876 performance is opti-
mized by operating the device at its maximum sample rate of
100 kSPS and digitally filtering the resulting bit stream to the
desired signal bandwidth. This succeeds in distributing noise
over a wider frequency range, thus reducing the noise density in
the frequency band of interest. This subject is discussed in the
pling rate. This is established by the Nyquist theorem, which
requires that a signal be sampled at a rate corresponding to at
least twice its widest bandwidth of interest in order to preserve
the information content. Oversampling is a conversion tech-
nique in which the sampling frequency is an integral (2 or more)
multiple of twice the frequency bandwidth of interest. In audio
applications, the AD1876 can operate at a 2
put is represented in the frequency spectrum from dc to the
Nyquist rate of the converter. Within this same spectrum are
higher frequency aliased noise components. Antialias, or low-
pass, filters are used at the input to the ADC to remove the por-
tion of these noise components attributed to high frequency
analog input noise. However, wideband noise contributed by the
AD1876 will not be reduced by the antialias filter. The AD1876
contributed noise is evenly distributed from dc to the Nyquist
rate, and this fact can be used to minimize its overall effect.
oversampling--sampling at a rate higher than defined by the
Nyquist theorem. This spreads the noise energy over a distribu-
tion of frequencies wider than the frequency band of interest,
and by judicious selection of a digital filter, noise frequencies
outside the bandwidth of interest may be eliminated. The pro-
cess of quantization inherently produces noise, known as quanti-
zation noise. The magnitude of this noise is a function of the
resolution of the converter, and manifests itself as a limit to the
theoretical signal-to-noise ratio achievable. This limit is de-
scribed by S/(N+D) = (6.02 n + 1.76 + 10 log F
ing at a 2
at the Nyquist conversion rate of 48 kSPS. Oversampling has
another advantage as well; the demands on the antialias filter are
ning the AD1876 at or near its maximum sampling rate of
100 kHz and digitally filtering the resulting spectrum to elimi-
nate undesired frequencies.
digital signal processor with the AD1876. The ADSP-2101 FO
(flag out) pin of serial port 1 (SPORT 1) is connected to the
SAMPLE line and is used to control acquisition of data. The
ADSP-2101 timer is used to provide precise timing of the FO
input for the AD1876. The clock should be programmed to be
approximately 2 MHz to comply with AD1876 specifications.
To minimize digital feedthrough, the clock should be disabled
(by setting Bit 14 in SPORT0 control register to 0) during data
acquisition. Since the clock floats when disabled, a pull-down
resistor of 12 k15 k
the conversion rate, the serial clock should be enabled immedi-
ately after SAMPLE is brought LOW (hold mode).
SPORT0 when a new data word is coming. SPORT0 should be
configured in normal, external, noninverting framing mode and
bit is received. To maximize the conversion rate, SAMPLE
should be brought HIGH immediately after the last data bit is
AD1876 and an ADSP-2101 signal processing microcomputer.
This system can analyze signals from dc to 50 kHz depending
on the sample rate. This is ideal for applications such as audio
analysis, but could also be applied to vibration analysis as well.
from two AD1876 audio ADCs, a signal processing microcom-
puter and two AD1856 audio DACs. Depending on the length
of the internal buffer which produces the delay, a variable delay
is possible. Other applications are also possible with only a
change in software. For example, a reverb or echo effect could
be generated as well.
AD1876 is to connect one or more AD1876s to an NPC
SM5805 digital filter. This device supplies all signals required to
operate the AD1876 at a 96 kHz sample rate, which is 2
filtered only by a low order analog filter. The AD1876 samples
the output of the filter at 2 F
off at 0.5 F
9. The start signal for the AD1876 (for 96 kSPS operation) is
provided by the S/H pin of the SM5805, and CLK is derived
from the BCC pin. Figure 10 illustrates the corresponding tim-