reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
120 dB Signal-to-Noise Ratio
102 dB D-Range Performance
1 mA Output Current
0.0012% THD + N
High Performance Compact Disc Players
Digital Audio Amplifiers
Digital Mixing Consoles
High Resolution Signal Processing
device provides a 20-bit DAC, 20-bit serial-to-parallel input
register and voltage reference. The digital portion of the
AD1862 is fabricated with CMOS logic elements that are pro-
vided by Analog Devices' BiMOS II process. The analog por-
tion of the AD1862 is fabricated with bipolar and MOS devices
as well as thin-film resistors.
produce extremely high performance audio playback. The de-
sign of the AD1862 incorporates a digital offset circuit which
improves low-level distortion performance. Low stress packag-
ing techniques are used to minimize stress-induced parametric
shifts. Stress-sensitive circuit elements are located in die areas
which are least affected by packaging stress. Laser-trimming of
initial linearity error affords extremely low total harmonic
distortion. Output glitch is also small, contributing to the over-
all high level of performance.
with the recommended two external noise-reduction capacitors,
it achieves 120 dB signal-to-noise ratio.
pins. A serial 20-bit, 2s complement data word is clocked into
the DAC, MSB first, by the external data clock. A latch-enable
signal transfers the input word from the internal serial input
at 17 MHz, allowing 16
sumer audio products such as the NPC SM5813 and SM5818.
digital crosstalk. Separate analog and digital common pins are
also provided. The AD1862 typically dissipates less than
range is guaranteed to be 25
Specifications subject to change without notice.
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . . . 0.3 to V
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1862 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Total Harmonic Distortion plus Noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the val-
ues of the harmonics and noise to the value of the fundamental
input frequency. It is usually expressed in percent (%) or deci-
distortion plus noise at 60 dB. In this case, an A-Weight filter
is used. The value specified for D-Range performance is the ra-
tio measured plus 60 dB.
performance and is usually expressed in nanoseconds (ns).
tude of the output with full-scale present to the amplitude of the
output when no signal is present. It is expressed in decibels (dB)
and measured using an A-Weight filter.
amplitude from the ideal output amplitude. It is determined by
measuring the amplitude of the output signal as the amplitude
of that output signal is digitally reduced to a low level. A perfect
D/A converter exhibits no difference between the ideal and ac-
tual amplitudes. Gain linearity is expressed in decibels (dB).
tual analog output from the ideal output when the 2s comple-
ment input code representing midscale is loaded in the input
register. The AD1862 is a current output D/A converter. There-
fore, this error is expressed in
DAC. Each device includes a voltage reference, a 20-bit DAC,
20-bit input latch and a 20-bit serial-to-parallel input register. A
special digital offset circuit, combined with segmentation cir-
cuitry, produces excellent THD+N and D-range performance.
performance of the AD1862 as high as possible. For example,
the voltage reference circuit is a low-noise, 9 volt bandgap cell.
This cell supplies the reference voltage to the bipolar offset cir-
cuit and the DAC. An external noise-reduction capacitor is con-
nected to NR1 to form a low-pass filter network.
amplifier of the DAC. By connecting an external noise-reduction
capacitor to NR2 output noise contributions from the control
portion of the DAC are similarly reduced. The noise-reduction
efforts result in a signal-to-noise ratio of 120 dB.
coder, R-2R topology and digital offset to produce low distor-
tion at all signal amplitudes. The digital offset technique shifts
the midscale output voltage (0 V) away from the MSB transition
of the device. Therefore, small amplitude signals are not af-
fected by an MSB change. An extra DAC cell is included to
avoid clipping the output at full scale.
put register and serial-to-parallel converter are fabricated with
CMOS logic gates. These gates allow the achievement of fast
switching speeds and low power consumption. Internal TTL-
to-CMOS converters are used to insure TTL and 5 V CMOS
(AGND) and digital ground (DGND). The analog ground pin
is the "high-quality" ground reference for the device. The ana-
log ground pin should be connected to the analog common
point in the system. The reference bypass capacitor, the nonin-
verting terminal of the current-to-voltage conversion op amp,
and any output loads should be connected to this point. The
digital ground pin returns ground current from the digital logic
portions of the AD1862 circuitry. This pin should be connected
to the digital common point in the system.
nected together at one point in the system.
cluding the voltage reference and control amplifier. The
TTL-to-CMOS level shifters. The
pins. Good engineering practice suggests that these capacitors
be placed as close as possible to the package pins and the com-
mon points. The logic supplies,
tion. Their correct connection is illustrated in Figure 8. Capacitor
C1 is connected between the pin labeled NR1 and analog com-
mon. C1 forms a low-pass filter element which reduces noise con-
this capacitor is a tantalum type with value of 10
possible. This will minimize the effects of parasitic inductance of
the leads and connections circuit connections.
PIN 1 IS "HIGH QUALITY" RETURN
FOR BIAS CAP.
negative analog supply, V
C2 should be chosen to be a tantalum capacitor with a value of
mately 10. Additional noise reduction can be gained by choos-
ing slightly higher values for C1 and C2 such as 22
external amplifier, in combination with the on-board feedback
resistor, is required to derive an output voltage. Figure 9 illus-
trates the proper connections for an external operational ampli-
fier. The output of the AD1862 is intended to drive the
summing junction of an external current-to-voltage conversion
op amp. Therefore, the voltage on the output current pin of the
AD1862 should be approximately the same as that on the
AGND pin of the device.
tional trimming. For example, if a user wishes to derive an out-
put voltage higher than the
to combine a standard value resistor with the feedback resistor
to achieve the appropriate output voltage swing. This technique
can be extended to include the choice of elements in the
deemphasis network, etc.
desirable signal produced during reconstruction and playback of
an audio waveform. The THD specification, therefore, provides
a direct method to classify and choose an audio DAC for a de-
sired level of performance.
a THD+N specification is realized. This specification indicates
all of the undesirable signal produced by the DAC, including
harmonic products of the test tone as well as noise.
formance. In this test procedure, a digital data stream represent-
ing a 0 dB, 20 dB or 60 dB sine wave is sent to the device
under test. The frequency of the waveform is 990.5 Hz. Input
data is sent to the AD1862 at an 8
verted to an output voltage by an external amplifier. Figure 10
illustrates the recommended test circuit. Deglitchers and trims
are not used during this test procedure. The automatic test
equipment digitizes 4096 samples of the output test waveform,
incorporating 23 complete cycles of the sine wave. A 4096 point
FFT is performed on the test data.
tone, and the noise components in the audio band, the total har-
monic distortion + noise of the device is calculated. The
AD1862 is available in two performance grades. The AD1862N
produces a maximum of 0.0025% THD+N at 0 dB signal lev-
els. The higher performance AD1862N-J produces a maximum
of 0.0016% THD+N at 0 dB signal levels.
following manner. The amplitude of a 0 dB signal is measured.
The device under test is then set to midscale output voltage (0
volts). The amplitude of all noise present to 30 kHz is mea-
sured. The SNR is the ratio of these two measurements. The
SNR figure for the AD1862 includes the output noise contrib-
uted by the NE5534 op amp used in the test fixture but does
not include the noise contributed by the low-pass filter used in
the test fixture.
performance AD1862N-J has a minimum SNR of 113 dB.
Should an application require improved distortion performance
under small and very small signal amplitudes (60 dB and
lower), an adjustment is possible. Two resistors and one poten-
tiometer form the adjustment network. Figure 11 illustrates the
correct configuration of the external components. Analog
Devices recommends that this adjustment be performed with
60 dB signal amplitudes or lower. Minor performance im-
provement is achieved with larger signal amplitudes such as
20 dB. Almost no improvement is possible when this adjust-
ment is performed with 0 dB signal amplitudes.
20-bit words with a serial, 2s complement, MSB first format.
Three signals must be present to achieve proper operation. They
are the data, clock and latch enable signals. Input data bits are
signal (CLK). The LSB is clocked in on the 20th clock pulse.
When all data bits are loaded, a low going latch enable (LE)
pulse updates the DAC input. Figure 12a illustrates the general
signal requirements for data transfer for the AD1862.
be met in order for the data transfer to be accomplished success-
fully. The input pins of the AD1862 are both TTL and 5 V
CMOS compatible, independent of the power supplies used in
the application. The input requirements illustrated in Figure
digital interpolation filter chips used in digital audio playback
systems. The AD1862 input clock will run at 17 MHz allowing
data to be transferred at a rate of 16
for high-end consumer and professional digital audio applica-
tions. Compact disc players, digital preamplifiers, digital musi-
cal instruments and sound processors benefit from the extended
dynamic range, low THD+Noise and high signal-to-noise ratio.
For the first time, the D/A converter is no longer the basic limi-
tation in the performance of a CD player.
consoles, digital tape recorders and multivoice synthesizers can
utilize the wide dynamic range and signal-to-noise ratio to
achieve greater performance. And, the AD1862's space saving
16-pin package contributes to compact system design. This per-
mits a system designer to incorporate more voices in multivoice
synthesizers, more tracks in multitrack tape recorders and more
channels in multichannel mixing consoles.
generation applications are equally well served by the AD1862.
formance CD player. Two AD1862s are used, one for the left
channel and one for the right channel. The CXD11XX chip de-
codes the digital data coming from the read electronics and
sends it to the SM5813. Input data is sent to each AD1862 by
the SM5813 digital interpolating filter. This device operates at
8 times oversampling. The NE5534 op amps are chosen for
current-to-voltage converters due to their low distortion and low
noise. The output filters are 5-pole designs. For the purpose of
clarity, all bypass capacitors have been omitted from the schematic.
In high-resolution applications, the combination of the 24-bit
architecture of the DSP56000 and the low noise and high reso-
lution of the AD1862 can produce a high-resolution, low-noise
processor must be inverted to be compatible with the input of
the AD1862. The exact architecture of the output low-pass filter
higher the oversampling rate, the fewer number of filter poles
are required to prevent aliasing.
dio, mixing or equalization equipment. Its resolution allows
24 dB of equalization to be performed on 16-bit input words
without signal truncation. Furthermore, up to sixteen 16-bit in-
put words can be mixed and output directly to the AD1862. In
this case, no loss of signal information would be encountered.
16-Pin DIP or SOIC Package
108 dB Signal-to-Noise Ratio
16-Pin DIP or SOIC Package
115 dB Channel Separation