audio playback subsystem. It comprises a variable rate
and continuous time analog filters, and analog output drive cir-
cuitry. Other features include an on-chip stereo attenuator and
mute, programmed through an SPI-compatible serial control
nous master clock capability. Previous
intended audio sample rate. The generation and management
of this high frequency synchronous clock is burdensome to the
board level designer. The analog performance of conventional
Locked Loop (PLL) which allows the master clock to be asyn-
chronous, and which also strongly rejects jitter on the sample
clock (left/right clock). The digital PLL allows the AD1859 to
be clocked with a single frequency (27 MHz for example) while
the sample frequency (as determined from the left/right clock)
can vary over a wide range. The digital PLL will lock to the
new sample rate in approximately 100 ms. Jitter components
15 Hz above and below the sample frequency are rejected by
6 dB per octave. This level of jitter rejection is unprecedented
in audio DACs.
essentially linear phase response, and with an option for external
analog de-emphasis processing. The clock circuit includes an
on-chip oscillator, so that the user need only provide an external
crystal. The oscillator may be overdriven, if desired, with an ex-
ternal clock source.
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Complete, Low Cost Stereo DAC System in a Single Die
64 Step (1 dB/Step) Analog Attenuator with Mute
Buffered Outputs with 2 k Output Load Drive
Rejects Sample Clock Jitter
94 dB Dynamic Range, 88 dB THD+N Performance
Option for Analog De-emphasis Processing with
Digital Phase Locked Loop Based Asynchronous Master
Flexible Serial Data Port (I
Single +5 V Supply
28-Pin SOIC and SSOP Packages
Digital Cable TV and Direct Broadcast Satellite Set-Top
High Definition Televisions, Digital Audio Broadcast
Digital Audio Workstations, Computer Multimedia
Performance of the right and left channels are identical (exclusive of "Interchannel Gain Mismatch" and "Interchannel Phase Deviation" specifications).
Attenuation setting is 0 dB.
Values in bold typeface are tested; all others are guaranteed, not tested.
conditions for extended periods may affect device reliability.
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1859 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
containing 8 bits of unsigned
data per channel. Used for
specifying channel specific
attenuation and mute.
data. Control input data must
be valid on the rising edge of
CCLK. CCLK may be continu-
ous or gated.
input is rising edge sensitive.
ing two channels of 16 or 18 bits
of twos complement data per
Need not run continuously; may
be gated or used in a burst
data. Must run continuously.
control zero. With IDPM1,
defines one of four serial input
trol one. With IDPM0, defines
one of four serial input modes.
control. Connect this signal HI
for 18-bit input mode, LO for
16-bit input mode.
pected output, expressed as a percentage.
two stereo channels, expressed in decibels.
temperature, expressed as parts-per-million (ppm) per
1 kHz sine-wave input on the other channel, expressed in decibels.
expressed as a phase difference in degrees between 1 kHz inputs.
p-p signal is applied to power supply pins, expressed in decibels
of full scale.
pear at the converter's output, expressed in seconds (s). More
precisely, the derivative of radian phase with respect to radian
frequency at a given frequency.
Specified as the difference between the largest and the smallest
group delays in the passband, expressed in microseconds (
noise in the passband (0 to 20 kHz), expressed in decibels (dB).
Dynamic range is measured with a 60 dB input signal and is
equal to (S/[THD+N]) + 60 dB. Note that spurious harmonics
are below the noise with a 60 dB input, so the noise level es-
tablishes the dynamic range. This measurement technique is
consistent with the recommendations of the Audio Engineering
Society (AES17-1991) and the Electronics Industries Association
of Japan (EIAJ CP-307).
fundamental input signal to the rms sum of all other spectral
components in the passband, expressed in decibels (dB) and
ation of the digital interpolation filter.
amplitude input signal frequencies within the passband, ex-
pressed in decibels.
tal interpolation filter to the degree specified by "stopband
connection. Bypass and decouple
the voltage reference with paral-
Use exclusively for bypassing and
decoupling of the FILT pin
output. Should be decoupled
externally for dc-coupling and level-
shifting. CMOUT should not have
any signal dependent load, or where
it will sink or source current.
for the left channel. Can be left
unconnected if de-emphasis is not
required in the target application.
for the right channel. Can be left
unconnected if de-emphasis is not
required in the target application.
placed in a low power consumption
"sleep" mode when this pin is held
LO. The AD1859 is reset on the
rising edge of this signal. The serial
control port registers are reset to
their default values. Connect HI
for normal operation.
emphasis circuit network is enabled
when this input signal is HI. This
circuit is typically used to impose a
output audio spectrum.
stereo analog outputs of the AD1859.
Deassert LO for normal operation.
Connect to one side of a quartz
crystal to this input, or connect to
an external clock source to over-
drive the on-chip oscillator.
side of a quartz crystal. Do not con-
nect if using the XTALI/MCLK
pin with an external clock source.
to analog +5 V supply.
to digital +5 V supply.
that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers and sample rate converters.
The serial data input port can be configured in left-justified,
MSB-first, twos-complement format. A power-down mode is
offered to minimize power consumption when the device is inac-
tive. The AD1859 operates from a single +5 V power supply. It
is fabricated on a single monolithic integrated circuit using a
the temperature range 40
architectures (no component trims, low cost CMOS process
technology, superb low level linearity performance) with the
advantages of conventional multibit R-2R resistive ladder audio
DACs (no requirement for any high frequency synchronous master
clocks [e.g., 256 or 384
AD1859 generates dramatically lower amounts of out-of-band
noise energy, which greatly reduces the requirement on post
DAC filtering. The required post-filtering is integrated on the
AD1859. The AD1859's multibit sigma-delta modulator is also
highly immune to digital substrate noise.
precedented jitter rejection feature. The bandwidth of the first
order loop filter is 15 Hz; jitter components on the input
left/right clock are attenuated by 6 dB per octave above and be-
low 15 Hz. Jitter on the crystal time base or MCLK input is re-
jected as well (by virtue of the on-chip switched capacitor filter),
but this clock should be low jitter because it is used by the DAC
to convert the audio from the discrete time (sampled) domain to
the continuous time (analog) domain. The AD1859 includes an
on-chip oscillator, so that the user need only provide an inexpen-
sive quartz crystal or ceramic resonator as an external time base.
to clock the data into the AD1859. The bit clock may, there-
fore, be asynchronous to the L/R clock. The left/right clock
(LRCLK) is both a framing signal, and the sample frequency input
to the digital phase locked loop. The left/right
sample rate, and it is the jitter on LRCLK that is rejected by the
digital phase locked loop. The SDATA input carries the serial
stereo digital audio in MSB first, twos-complement format.
data, i.e., to increase the sample rate so that the attenuation re-
quirements on the analog reconstruction filter are relaxed. The
AD1859 interpolator increases the input data sample rate by a
variable factor depending on the sample frequency of the incom-
ing digital audio. The interpolation is performed using a multi-
stage FIR digital filter structure. The first stage is a droop
equalizer; the second and third stages are half-band filters; and
implementation is multiplier-free, i.e., the multiplies are per-
formed using shift-and-add operations.
traditional single bit sigma-delta modulator has two levels of quan-
tization, the AD1859's has 17 levels of quantization. Traditional
single bit sigma-delta modulators sample the input signal at 64
times the input sample rate; the AD1859 samples the input sig-
nal at nominally 128 times the input sample rate. The addi-
tional quantization levels combined with the higher oversampling
ratio means that the AD1859 DAC output spectrum contains
dramatically lower levels of out-of-band noise energy, which is a
major stumbling block with more traditional single bit sigma-
delta architectures. This means that the post-DAC analog re-
construction filter has reduced transition band steepness and
attenuation requirements, which equates directly to lower phase
distortion. Since the analog filtering generally establishes the
noise and distortion characteristic of the DAC, the reduced
requirements translate into better audio performance.
they are essentially free of stability (and therefore potential loop
oscillation) problems. They are able to use a wider range of the
voltage reference, which can increase the overall dynamic range
of the converter.
multibit sigma delta converters is the nonlinearity of the passive
circuit elements used to sum the quantization levels. Analog
Devices has developed (and been granted patents on) a revolu-
tionary architecture which overcomes the component linearity
problem that otherwise limits the performance of multibit sigma
delta audio converters. This new architecture provides the
AD1859 with the same excellent differential nonlinearity and
linearity drift (over temperature and time) specifications as
single bit sigma-delta DACs.
vantage; it has a high immunity to substrate digital noise. Sub-
strate noise can be a significant problem in mixed-signal
designs, where it can produce intermodulation products that
fold down into the audio band. The AD1859 is approximately
eight times less sensitive to digital substrate noise (voltage refer-
ence noise injection) than equivalent single bit sigma-delta
modulator based DACs.
tended to further reduce the quantization noise introduced by
the multibit DAC. The dither has a triangular Probability Dis-
tribution Function (PDF) characteristic, which is generally con-
sidered to create the most favorable noise shaping of the residual
quantization noise. The AD1859 is among the first low cost, IC
audio DACs to include dithering.
crete time low-pass filter followed by a first-order analog con-
tinuous time low-pass filter. These filters eliminate the need for
any additional off-chip external reconstruction filtering. This
on-chip switched capacitor analog filtering is essential to reduce
the deleterious effects of any remaining master clock jitter.
enables de-emphasis when it is asserted HI. Two analog out-
puts, EMPL (Pin 3) and EMPR (Pin 26) are used to switch the
required analog components into the output stage of the AD1859.
An analog implementation of de-emphasis is superior to a digital
implementation in several ways. It is generally lower noise, since
digital de-emphasis is usually created using recursive IIR filters,
which inject limit cycle noise. Also the digital de-emphasis is be-
ing applied in front of the primary analog noise generation source,
the DAC modulator, and its high frequency noise contributions
are not attenuated. An analog de-emphasis circuit is down-
stream from the relatively "noisy" DAC modulator and thus pro-
vides a more effective noise reduction role (which was the original
intent of the emphasis/de-emphasis scheme). A final key advan-
tage of analog de-emphasis is that it is sample rate invariant, so
that users can fully exploit the sample rate range of the AD1859
and simultaneously use de-emphasis. Digital implementations gen-
erally only support fixed, standard sample rates.
(on the LRCLK Pin 13) in 100 ms to 200 ms. The digital PLL
is initially in "fast" mode, with a wide lock capture bandwidth.
"slow" mode as phase lock is gradually obtained. The loop
bandwidth is 15 Hz in slow mode. Since the loop filter is first
order, the digital PLL will reject jitter on the left/right clock
above 15 Hz, with an attenuation of 6 dB per octave. The jitter
rejection frequency response is shown in Figure 1.
Serial Data Input Port
determine the input sample rate. LRCLK must run continu-
ously and transition twice per stereo sample period (except in
the left-justified DSP serial port style mode, when it transitions
four times per stereo sample period). The bit clock (BCLK) is
edge sensitive and may be used in a gated or burst mode (i.e., a
stream of pulses during data transmission followed by periods of
inactivity). The bit clock is only used to write the audio data
into the serial input port. It is important that the left/right clock
is "clean" with monotonic rising and falling edge transitions and
no excessive overshoot or undershoot which could cause false
clock triggering of the AD1859.
twos-complement, MSB-first format. The left channel data
field always precedes the right channel data field. The input
data consists of either 16 or 18 bits, as established by the 18/16
input control (Pin 8). All digital inputs are specified to TTL
logic levels. The input data port is configured by control pins.
mode configuration of the input data port. IDPM0 and IDPM1
program the input data port mode as follows:
(See Figure 5)
left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is delayed 14-bit clock periods
(in 18-bit input mode) or 16-bit clock periods (in 16-bit input
mode) from an LRCLK transition, so that when there are 64
BCLK periods per LRCLK period, the LSB of the data will be
right-justified to the next LRCLK transition.
edge of BCLK. The MSB is left-justified to an LRCLK transition
but with a single BCLK period delay. The I
left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left-justified to an LRCLK
transition, with no MSB delay. The left-justified mode can be
used in either the 16-bit or the 18-bit input mode.
LRCLK must pulse HI for at least one bit clock period before
the MSB of the left channel is valid, and LRCLK must pulse HI
again for at least one bit clock period before the MSB of the
right channel is valid. Data is valid on the falling edge of
BCLK. The left-justified DSP serial port style mode can be
used in either the 16-bit or the 18-bit input mode. Note that in
this mode, it is the responsibility of the DSP to ensure that the
left data is transmitted with the first LRCLK pulse, and that the
right data is transmitted with the second LRCLK pulse, and
that synchronism is maintained from that point forward.
to an LRCLK transition. LRCLK is HI for the left channel,
and LO for the right channel. Data is valid on the rising edge of
BCLK. Packed mode can be used when the AD1859 is pro-
grammed in either right-justified or left-justified mode. Packed
mode is shown in Figure 6.
(Serial Peripheral Interface) is a serial port protocol popularized
by Motorola's family of microcomputer and microcontroller
products. The write-only serial control port gives the user ac-
cess to channel specific mute and attenuation. The AD1859
serial control port consists of three signals, control clock CCLK
(Pin 19), control data CDATA (Pin 20), and control latch
CLATCH (Pin 21). The control data input (CDATA) must be
valid on the control clock (CCLK) rising edge, and the control
clock (CCLK) must only make a LO to HI transition when
there is valid data. The control latch (CLATCH) must make a
LO to HI transition after the LSB has been clocked into the
AD1859, while the control clock (CCLK) is inactive. The tim-
ing relation between these signals is shown in Figure 7.
Left Channel = LO
Normal = LO
00 0001 = 1.0dB
00 0010 = 2.0dB
00 0011 = 3.0dB
00 0100 = 4.0dB
00 0101 = 5.0dB
00 0110 = 6.0dB
00 0111 = 7.0dB
00 1000 = 8.0dB
11 1101 = 61.0dB
11 1110 = 62.0dB
11 1111 = 63.0dB
and is unsigned. There is a control register for the left channel
and a control register for the right channel, as distinguished by
the MSB (DATA7). The bits are assigned as shown in Figure 8.
ister have identical power up and reset default settings. DATA6,
the Mute control bit, reset default state is LO, which is the nor-
mal (nonmuted) setting. DATA5:0, the Atten5 through Atten0
control bits, have a reset default value of 00 0000, which is an
attenuation of 0.0 dB (i.e., full scale, no attenuation). The intent
with these reset defaults is to enable AD1859 applications with-
out requiring the use of the serial control port. For those users
that do not use the serial control port, it is still possible to mute
the AD1859 output by using the external MUTE (Pin 7) signal.
It is recommended that the output be muted for approximately
1000 input sample periods during power-up or following any
radical sample rate change (>5%) to allow the digital phase
locked loop to settle.
serial data input port timing. Changes made to the attenuator
level will be updated on the next edge of the LRCLK after the
CLATCH write pulse. The AD1859 has been designed to re-
solve the potential for metastability between the LRCLK edge
and the CLATCH write pulse rising edge. The attenuator set-
ting is guaranteed to be valid even if the LRCLK edge and the
CLATCH rising edge occur essentially simultaneously.
by either an external clock source applied to XTALI/MCLK or
by connecting a crystal across the XTALI/MCLK and XTALO
pins, and using the on-chip oscillator. If a crystal is used, it
should be fundamental-mode and parallel-tuned. Figure 9
shows example connections.
LRCLK input) supported by the AD1859 is a function of the
master clock rate (i.e., the crystal frequency or external clock
source frequency) applied. The highest sample rate supported
can be computed as follows:
a 27 MHz MCLK or crystal frequency supports audio sample
rates from approximately 28 kHz to 52 kHz.
CLOCK SAMPLE FREQUENCY kHz
By asserting the MUTE (Pin 7) signal HI, both the left channel
and the right channel are muted. As an alternative, the user can
assert the mute bit in the serial control registers HI for indi-
vidual mute of either the left channel or the right channel. The
muting and unmuting the device. The AD1859 includes a zero
crossing detector which attempts to implement attenuation
changes on waveform zero crossings only. If a zero crossing is
not found within 1024 input sample periods (approximately
23 ms at 44.1 kHz), the attenuation change is made regardless.
such as the Analog Devices SSM2142 should be used. The
analog output is generally ac coupled with a 10
Figure 17. It is possible to dc couple the AD1859 output into an
op amp stage using the CMOUT signal as a bias point.
lishes the output voltage range. The nominal value of this refer-
ence is +2.25 V which corresponds to a line output voltage
swing of 3 V p-p. The line output signal is centered around a
voltage established by the CMOUT (common mode) output
(Pin 1). The reference must be bypassed both on the FILT in-
put (Pin 28) with 10
FGND ground, and the CMOUT pin must use the AGND
ground. The on-chip voltage reference may be overdriven with
an external reference source by applying this voltage to the
FILT pin. CMOUT and FILT must still be bypassed as shown
in Figures 17 and 18. An external reference can be useful to
calibrate multiple AD1859 DACs to the same gain. Reference
bypass capacitors larger than those suggested can be used to im-
prove the signal-to-noise performance of the AD1859.
sumed by the AD1859. When PD/RST is held LO, the AD1859
is placed in a low dissipation power-down state. When PD/RST
is brought HI, the AD1859 becomes ready for normal operation.
The master clock (XTALI/MCLK, Pin 16) must be running for
a successful reset or power-down operation to occur. The PD/RST
signal must be LO for a minimum of four master clock periods
(approximately 150 ns with a 27 MHz XTALI/MCLK
AD1859 is reset. All registers in the AD1859 digital engine (se-
rial data port, interpolation filter and modulator) are zeroed, and
the amplifiers in the analog section are shorted during the reset
operation. The two registers in the serial control port are initial-
ized to their default values. The user should wait 100 ms after
bringing PD/RST HI before using the serial data input port and
the serial control input port in order for the digital phase locked
loop to re-acquire lock. The AD1859 has been designed to
minimize pops and clicks when entering and exiting the power-
normally connected HI or LO to establish the operating state of
the AD1859. They can be changed dynamically (and asynchro-
nously to the LRCLK and the master clock) as long as they are
stable before the first serial data input bit (i.e., the MSB) is pre-
sented to the AD1859.
Interface to MPEG Audio Decoders
ADSP-21xx family of DSP chips, for which several MPEG
audio decode algorithms are available. The ADSP-21xx supports
16 bits of data using a left-justified DSP serial port style format.
ments TMS320AV110 MPEG audio decoder IC. The
TMS320AV110 supports 18 bits of data using a right-justified
MPEG audio decoder IC. The L64111 supports 16 bits of data
using a left-justified output format.
MPEG audio decoder IC. The SAA2500 supports 18 bits of
data using an I
DSP chip, which can act as an MPEG audio or AC-3 audio
decoder. The ZR38000 supports 16 bits of data using a left-
justified output format.
Microsystems CL480 MPEG system decoder IC. The CL480
supports 16 bits of data using a right-justified output format.
are shown in Figure 17. Figure 17 illustrates a connection dia-
gram for systems which do not require de-emphasis support.
The recommended circuit connection for system including de-
emphasis is shown in Figure 18.
FOR EXTERNAL USE
FOR EXTERNAL USE
plane, with the digital pins over the digital ground plane, and
the analog pins over the analog ground plane. The split should
occur between Pins 6 and 7 and between Pins 22 and 23 as
shown in Figure 19. The ground planes should be tied together
at one spot underneath the center of the package with an ap-
proximately 3 mm trace. This ground plane strategy minimizes
RF transmission and reception as well as maximizes the AD1859's
analog audio performance.
minimum bit clock HI pulse width is t
mum control clock HI pulse width is t
ing is shown in Figure 23. The minimum MCLK period is t
of the AD1859 as measured by an Audio Precision System One.
Signal-to-Noise (dynamic range) and THD+N performance is
shown under a range of conditions. Note that there is a small
variance between the AD1859 analog performance specifica-
tions and some of the performance plots. This is because the
Audio Precision System One measures THD and noise over a
specified over a 20 Hz to 20 kHz bandwidth (i.e., the AD1859
performs slightly better than the plots indicate). Figure 28
shows the power supply rejection performance of the AD1859.
The channel separation performance of the AD1859 is shown in
Figure 29. The AD1859's low level linearity is shown in Figure
30. The digital filter transfer function is shown in Figure 31.
THD+N vs dBFS @ 1kHz
ing Time Domain Plot Bandlimited to 22 kHz
Devices SSM2017 and SSM2142 components. Figure 33
illustrates a "Numerically Controlled Oscillator" (NCO) that
can be implemented in programmable logic or a system ASIC to
provide the synchronous bit and left/right clocks from 27 MHz
for MPEG audio decoders. Note that the bit clock and left/right
clock outputs are highly jittered, but this jitter should be
this clock jitter (using these signals to clock audio data from their
output serial port, and perhaps to decrement their audio/video
synchronization timer), while the AD1859 will reject the left/right
clock jitter by virtue of its on-chip digital phase locked loop.
Contact Analog Devices Computer Products Division Customer
Support at (617) 461-3881 or email@example.com for more
information on this NCO circuit.
SELECT R BUS WHEN K > N (MSB = 1)