reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Digital Signal Mixing
On-Chip Speaker and Headphone Drive Capability
Programmable Gain and Attenuation
On-Chip Signal Filters
Analog Output Low-Pass
44-Lead PLCC and TQFP Packages
Operation from +5 V and Mixed +5 V/+3.3 V Supplies
Serial Interface Compatible with ADSP-21xx Fixed-
additional external components. Dynamic range exceeds 80 dB
over the 20 kHz audio band. Sample rates from 5.5 kHz to
48 kHz are supported from external crystals, from an external
clock, or from the serial interface bit clock.
A software controlled programmable gain stage allows
independent gain for each channel going into the ADC. The
ADCs' output can be digitally mixed with the DACs' input.
available over a single bidirectional serial interface that also sup-
ports 16-bit digital input to the DACs and control information.
The AD1849K can accept and generate 8-bit
DAC channel. Nyquist images and shaped quantization noise
are removed from the DACs' analog stereo output by on-chip
switched-capacitor and continuous-time filters. Two independent
stereo pairs of line-level (or one line-level and one headphone)
outputs are generated, as well as drive for a monaural (mono)
the key audio data conversion and control functions into a single
integrated circuit. The AD1849K is intended to provide a com-
plete, single-chip audio solution for multimedia applications
requiring operation from a single +5 V supply. External signal
path circuit requirements are limited to three low tolerance
capacitors for line level applications; anti-imaging filters are
incorporated on-chip. The AD1849K includes on-chip monaural
Read Both Channels)
39 dB and 60 dB)
0 to 0.45
Supply Pins, Both ADCs and DACs)
Specifications subject to change without notice.
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1849K features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Level if MB = 1)
Level if MB = 1)
intended as a general introduction to the capabilities of the
device. As much as possible, detailed reference information has
been placed in "Control Registers" and other sections. The user
is not expected to refer repeatedly to this section.
line-level and mic-level inputs. These analog stereo signals are
multiplexed to the internal programmable gain amplifier (PGA)
stage. The mic inputs can be amplified by +20 dB prior to the
PGA to compensate for the voltage swing difference between
line levels and typical condenser microphones. The mic inputs
can bypass the +20 dB fixed gain block and go straight to the
input multiplexer, which often results in an improved system
selectable gains for each channel from 0 to 22.5 dB in +1.5 dB
steps. The Codec can operate either in a global stereo mode or
in a global mono mode with left-channel inputs appearing at
both channel outputs.
for anti-aliasing the analog input because of the ADC's high 64
times oversampling ratio. The ADCs include linear-phase digital
decimation filters that low-pass filter the input to 0.45
independent control of each DAC channel from 0 dB to 94.5 dB
in 1.5 dB steps plus full digital mute. The anti-imaging inter-
polation filter oversamples by 64 and digitally filters the higher
frequency images. The DACs'
outputs are then filtered in the analog domain by a combination
of switched-capacitor and continuous-time filters. They remove
the very high frequency components of the DAC bitstream
output, including both images at the oversampling rate and
shaped quantization noise. No external components are required.
Phase linearity at the analog output is achieved by internally
compensating for the group delay variation of the analog output
stream. Changes in DAC output level take effect only on zero
crossings of the digital signal, thereby eliminating "zipper"
noise. Each channel has its own independent zero-crossing
detector and attenuator change control circuitry. A timer
guarantees that requested volume changes will occur even in the
absence of an input signal that changes sign. The time-out
period is 10.7 milliseconds at a 48 kHz sampling rate and 64
milliseconds at an 8 kHz sampling rate (Time-out [ms]
digitized analog input with the analog output (prior to digitiza-
tion). The digital output from the ADCs going out of the serial
data port is unaffected by the monitor mix. Along the monitor
mix datapath, the 16-bit linear output from the ADCs is
attenuated by an amount specified with control bits. Both
channels of the monitor data are attenuated by the same
amount. (Note that internally the AD1849K always works with
16-bit PCM linear data, digital mixing included; format
conversions take place at the input and output.)
"0" implies no attenuation, while a "14" implies 84 dB of
attenuation. Specifying full scale "15" completely mutes the
monitor datapath, preventing any mixing of the analog input
with the digital input. Note that the level of the mixed output
signal is also a function of the input PGA settings since they
affect the ADCs' output.
input data prior to the DACs' datapath attenuators. Because
both stereo signals are mixed before the output attenuators, mix
data is attenuated a second time by the DACs' datapath
attenuators. The digital sum of digital mix data and DAC input
data is clipped at plus or minus full scale and does not wrap
one monaural (mono) speaker output are available at external
pins. Each of these outputs can be independently muted.
Muting either the line-level stereo output or the headphone
stereo output mutes both left and right channels of that output.
When muted, the outputs will settle to a dc value near
CMOUT, the midscale reference voltage. The mono speaker
output is differential. The chip can operate either in a global
stereo mode or in a global mono mode with left channel inputs
appearing at both outputs.
complement linear PCM, 8-bit unsigned linear PCM, 8-bit
ferred MSB first. Sixteen-bit linear data output from the ADCs
and input to the DACs is in twos-complement format. Eight-bit
data is always left-justified in 16-bit fields; in other words, the
MSBs of all data types are always aligned; in yet other words,
full-scale representations in all three formats correspond to
equivalent full-scale signals. The eight least-significant bit
positions of 8-bit linear and companded data in 16-bit fields are
ignored on input and zeroed on output.
dynamic range. Eight-bit PCM can represent 48 dB of dynamic
of precision is compensated for by an increase in dynamic range
to 64 dB and 72 dB, respectively.
linear representation, according to whether
bits. A-law data expanded requires 13 bits, see Figure 1.
compressed to the format specified prior to output. See Figure 2.
Internally, the AD1849K always uses 16-bit linear PCM
representations to maintain maximum precision.
analog and digital supplies are recommended for optimal
performance, though excellent results can be obtained in single
supply systems. A voltage reference is included on the Codec
and its 2.25 V buffered output is available on an external pin
(CMOUT). The CMOUT output can be used for biasing op
amps used in dc coupling. The internal reference is externally
bypassed to analog ground at the V
DAC and ADC offsets. The autocalibration sequence is
initiated in the transition from Control Mode to Data Mode,
regardless of the state of the AC bit. The user should specify
that analog outputs be muted to prevent undesired outputs.
Monitor mix will be automatically disabled by the Codec.
the ADCs is meaningless and the ADI bit is asserted. Serial data
inputs to the DACs are ignored. Even if the user specified the
muting of all analog outputs, near the end of the autocalibration
sequence, dc analog outputs very close to CMOUT will be
produced at the line outputs and mono speaker output.
AD1849K leaves the reset state (i.e.,
leaving power-down mode to delay the onset of the autocalibration
sequence until after the voltage reference has settled.
system testing. The monitor mix datapath is always available for
loopback test purposes. Additional loopback tests are enabled by
setting the ENL bit (Control Word Bit 33) to a "1."
bit (Control Word Bit 32) to a "1" when ENL is a "1." In this
mode, the DACs' analog outputs are re-input to the PGAs prior
to the ADCs, allowing digital inputs to be compared to digital
outputs. The monitor mix will be automatically disabled by the
Codec during D-A-D loopback. The analog outputs can be
individually attenuated, and the analog inputs are internally
disconnected. Note that muting the line 0 output mutes the
looped-back signal in this mode.
(Control Word Bit 32) to a "0" when ENL is a "1." In this
mode, the control and data bit pattern presented on the SDRX
pin is echoed on the SDTX pin with a two frame delay, allowing
the host controller to verify the integrity of the serial interface
starting on the third frame after D-D loopback is enabled.
During digital loopback mode, the output DACs are
generate a wide range of sample rates. The oscillators for these
crystals are on the AD1849K, as is a multiplexer for selecting
between them. They can be overdriven with external clocks by
the user, if so desired. The recommended crystal frequencies are
16.9344 MHz and 24.576 MHz. From them the following sample
rates can be internally generated: 5.5125, 6.615, 8, 9.6, 11.025,
16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1, 48 kHz.
Regardless of clock input source, a clock output of 256
serial port's bit clocks are selected to drive the AD1849K's
internal operation, they should be low jitter clocks. If no
external clock will be used, Analog Devices recommends tying
the clock input pin (CLKIN) to ground. If either external
crystal is not used, Analog Devices recommends tying its input
(CIN1 and/or CIN2) to ground.
information is also embedded in the data stream when in Data Mode. (See Figure 8.) Control bits can also be read back for system
verification. Operation of the AD1849K is determined by the state of these control bits. The 64-bit serial Control Mode and Data
Mode control registers have been arbitrarily broken down into bytes for ease of description. All control bits initialize to default states
Full-scale line 1 output is 4.0 V p-p.
Full-scale mono speaker output is 8.0 V p-p.
Full-scale line 1 output is 2.0 V p-p.
Full-scale mono speaker output is 4.0 V p-p.
Autocalibration will always occur on the Control-to-Data mode transition. The AC bit is ignored. Autocalibration
requires an interval of 194 frames. Offsets for all channels of ADC and DAC are zeroed. The user should specify that
analog outputs are muted to prevent undesired outputs, i.e., OM0 = "0," OM1 = "0," and SM ="0." Monitor mix will
be automatically disabled by the Codec.
external clock source is used, it should be applied to the crystal input pin (CIN1 or CIN2), and the crystal output pin
(COUT1 or COUT2) should be left unconnected. The external clock source need not be at the recommended crystal
frequencies, and it will be divided down by the selected Divide Factor.
(External clock must be stable and valid within 2000 periods after it is selected.)
providing the 256
internal Codec operation, slave mode is effectively selected, regardless of the contents of MS.
modes, this byte contains the left audio data sample. In mono mode, only the left audio data is used. MSB first format is used in all
modes, and twos-complement coding is used in 16-bit linear PCM mode.
modes, this byte is ignored on input, zeroed on output. In mono mode, only the left audio data is used. MSB first format is used in
all modes, and twos-complement coding is used in 16-bit linear PCM mode.
modes, this byte contains the right audio data sample. In mono mode, this byte is ignored on input, zeroed on output. MSB first
format is used in all modes, and twos complement coding is used in 16-bit linear PCM mode.
modes, this byte is not used. In mono mode, this byte is ignored on input, zeroed on output. MSB first format is used in all modes,
and twos-complement coding is used in 16-bit linear PCM mode.
93 dB of attenuation. Attenuation = 1.5 dB
ADCs is meaningless.
represents 93 dB of attenuation. Attenuation = 1.5 dB
"sticky," i.e., it remains set until explicitly cleared by writing a "0" to OVR. A "1" written to OVR is ignored,
allowing OVR to remain "0" until an overrange condition occurs.
(0 dB gain).
Gain = 1.5 dB
is 6 dB; "14" represents an attenuation of both channels of the ADCs' output along the monitor datapath of
84 dB. Mix attenuation = 6 dB
Gain = 1.5 dB
Upon coming out of
Output 8.0 V p-p
Mode get reset to the defaults above (except PIO). The control registers that can be changed in Control Mode will have the values
they were just assigned. The subset of the above list of control registers that are assigned default values on the transition from
Control Mode to Data Mode are:
serial streams always reflect the values most recently read from the external PIO pins. (See "Parallel I/O Bits" below for timing
details.) A Control-to-Data Mode transition is no exception.
externally supplied serial bit clock (SCLK) as the clock source. An external device must supply the serial bit clock and the chaining word
input signal (TSIN) initially. (See "Codec Startup, Modes, and Transitions" below for more details.)
fer of both data and control information. This interface is simi-
lar to AT&T's Concentrated Highway Interface (CHI), allowing
simple connection with ISDN and other telecommunication
devices. The AD1849K's implementation also allows a no-glue
direct connection to members of Analog Devices' family of
fixed-point DSP processors, including the ADSP-2101, the
ADSP-2105, the ADSP-2111, and the ADSP-2115.
plexing. Up to four AD1849K Codecs or compatible devices
can be daisy-chained on the same serial lines. A "frame" can
consist of one, two, or four 64-bit "words." Thus, frames can be
64, 128, or 256 bits in length as specified by the FSEL bits in
Control Byte 3. Only 64 bits of each frame, a "word," contain
meaningful data and/or control information for a particular
Codec. See Figure 4 below.
Control Words. The proper interpretation of a word is deter-
mined by the state of the asynchronous Data/Control (D/
modes require an adherence to a handshaking protocol to pre-
vent ambiguous bus ownership. The Data/ Control transition
protocol is described below in a separate section.
serial data receive (SDRX) input pin. The serial data transmit
(SRTX) pin, the serial data bit clock (SCLK) pin, the frame
sync output (FSYNC) pin, the chaining word input (TSIN) pin,
and the chaining word output (TSOUT) pin. The AD1849K
can operate in either master mode--in which case SCLK and
FSYNC are outputs and TSIN is an input--or in slave mode--
in which case SCLK and TSIN are inputs and FSYNC is three-
stated. If the AD1849K is in master mode, the internally
selected clock source is used to drive SCLK and FSYNC. Note
that in Control Mode, the Codec always behaves as a slave,
regardless of the current state of the MS (Master/Slave) bit.
are summarized in Figure 5.
Codec performance is improved with a clean clock source, and
in many systems the lowest jitter clocks available will be those
generated by the Codec's internal oscillators. Conversely, SCLK
in many systems will be the noisiest source. The master/SCLK
clock source combination is impossible because selecting SCLK
as the clock source overrides the MS control bit, forcing slave
mode. (The SCLK pin cannot be driving out if it is simulta-
neously receiving an external clock.)
the serial interface is in slave mode provided that all clocks
applied to the AD1849K SoundPort Codec are derived from the
same external source. Precise phase alignment of the clocks is
not necessary, rather the requirement is that there is no
frequency drift between the clocks.
the number of bits per frame selected (FSEL) and the sampling
Data outputs (except PIO) begin driving on the rising edge of
SCLK and are always valid well before the falling edge of
beginning of its word within a frame in both slave and master
modes. The master mode Codec will generate a FSYNC output
which indicates the beginning of a frame. In single Codec
systems, the master's FSYNC output should be tied to the
master's TSIN input to indicate that the beginning of the frame
is also the beginning of its word. In multiple Codec daisy-chain
systems, the master's FSYNC output should be tied to the
TSIN input of the Coded (either the master or one of the
slaves) which is intended to receive the first word in the frame.
FSYNC and TSIN are completely independent, and nothing
about the wiring of FSYNC to TSIN is determined by master or
slave status (i.e., the master can own any one of the words in the
frame). The master Codec's FSYNC can also be tied to all of
the slave Codecs' FSYNC pins. When a slave, a Codec's
FSYNC output is three-stated. Thus, it can be connected to a
master's FSYNC without consequence. See "Daisy-Chaining
Multiple Codecs" below for more details.
sampling frequency, F
an AD1849K's internal ADCs and DACs and its serial interface
circuitry. If, for example, a Codec has been programmed for two
words per frame (FSEL = "1"), then it will trigger the data
converters and transfer data between the converters and the
interface every 128 SCLKs. The TSIN input signals the Codec
where its word begins within the frame. In Control Mode, frame
size is irrelevant to the operation of any particular Codec; TSIN
and TSOUT are sufficient to convey all the information
transition of TSIN defines the beginning of the word to occur at
the next rising edge of SCLK (for driving output data). The
LO-to-HI transition is defined by consecutive LO and HI
samples of TSIN at the falling edges of SCLK. Both input and
output data will be valid at the immediately subsequent falling
edge of SCLK. See Figures 6 and 7.
"don't care"; its state will be ignored until one SCLK period
before the end of the current word.
OR DATA BYTE 1,
BIT 7 OUTPUT
OR DATA BYTE 8,
BIT 0 OUTPUT
specified in "Control Register Defaults." It will be in the mode
specified by the D/
transitions to Control Mode after initialization are expected to
be relatively infrequent. Control information that is likely to
change frequently, e.g., gain levels, is transmitted along with the
data in Data Mode. See Figure 8 for a complete map of the data
and control information into the 64-bit Data Word and the
64-bit Control Word.
sizes in multiples of 64 bits. The serial data is time-division
multiplexed (TDM), allocating each Codec its own 64-bit word
in the frame.
are the word chaining input (TSIN) and the word chaining out-
put (TSOUT ). As described above, TSIN is used to indicate
the position of the first bit of a particular Codec's 64-bit word
within the total frame.
Codec during the transmission of the last bit of its 64-bit word.
The first device in any Codec chain uses an externally generated
or self-generated FSYNC signal as an input to TSIN. The
TSOUT of the first Codec is wired directly to the TSIN of the
second Codec and so on. The waveform of TSOUT is a pulse of
one SCLK period in duration. All Codecs share the same
SCLK, FSYNC, SDRX, and SDTX lines since they are select-
ing different words from a common frame.
TSOUT. Thus, a Codec can be added or removed from the
chain simply by using the PDN pin. See "Reset and Power
Down" below for more details. See Figure 9 for an illustration
of daisy-chained Codecs.
mode without contention. All other Codecs must be in slave
mode, receiving SCLK and TSIN externally.
alternative, it is possible to connect the CLKOUT pin of the
master Codec to the CLKIN pins of the slaves, so that the sam-
ple frequency selected by the master (from one of its two crys-
tals) will be automatically applied to the slaves. The master
must be programmed for the desired sample frequency and the
correct number of bits per frame. The slaves must be pro-
grammed for CLKIN as the clock source, the correct number of
puts will be three-stated and thus can be connected to the
master's FSYNC without contention.
contrast, if the master Codec's CLKOUT is used as the clock
source, then it can run at either 256
"parallel I/O," PIO1:0. This provides a convenient mechanism
for transferring signaling information between the serial data
and control streams and the external pair of bidirectional pins
also named "PIO1" and "PIO0." The states of the parallel I/O
bits and pins do not affect the internal operation of the Codec in
any way; their exclusive use is for system signaling.
nally. They can be read (through serial output data) in either
Control or Data Mode and can be written (through serial input
data) in Data Mode exclusively. The values in the PIO field of
the Control Word serial input in Control Mode will be ignored.
An external device may drive either PIO pin LO even when
written HI by the Codec, since the pin outputs are open-drain.
Thus, a PIO value read back as a serial output bit may differ
from the value just written as a serial input bit.
SCLK periods before the first PIO bit is transmitted out over
the serial interface. In Data Mode, the PIO pins are sampled as
Bit 20 starts to be driven out. In Control Mode, the PIO pins
are sampled as Bit 36 starts being driven out. Timing para-
meters are as shown in Figure 7; PIO pin input data is relative
to the rising edge of SCLK. (Note that only the PIO pins are
read on SCLK rising edges.)
the input Data Word are read (Data Mode only). They are
driven on the falling edge of SCLK (unlike any other output).
The PIO data bits in the input are located at Bits 15 and 14 in
the Data Word and at Bits 31 and 30 in the Control Word
(Figure 8). Due to the five (5) SCLK period delay, the PIO pins
will be driven out with new values for Data Mode on the SCLK
falling edge when Bit 8 is read in, and for Control Mode on the
SCLK falling edge when Bit 24 is read in.
The AD1849K Stereo Codec can be reset by either of two
closely related digital input signals,
immediately echo whatever signal is applied to TSIN during
power down. This feature allows a very simple system test to
detect "life" even in a power-down state. It also allows the user
to selectively shut off Codecs in a daisy chain by powering down
the unwanted Codecs. The down-stream Codecs will simply
move up a word position in frame. The second difference is that
power consumption will be lower in power-down mode than in
exclusive reset mode. The CMOUT and LOUT1C pins will not
supply current while the AD1849K is in the power-down state
since all outputs collapse to ground.
power supplies and the voltage reference to settle. Any time
RESET is asserted during normal operation, it should remain
asserted for a minimum of 100 ns to insure a complete reset.
Note that an autocalibration sequence will always occur when
RESET is deasserted, in addition to on the Control Mode to
Data Mode transition.
Control pin (D/
register defaults are desired for Codec operation, it is possible to
go directly from reset or power down to Data Mode and begin
want to change the control register defaults by transmitting a
Control Word in Control Mode. The user of the AD1849K
SoundPort Codec can also enter Control Mode at any time
during normal Data Mode operation. The D/
determined solely by the behavior of the TSIN and TSOUT
signals. Each Codec by itself does not care where the frame
boundaries fall as defined by the system. The contents of the
frame size select (FSEL1:0, Control Word Bits 43 and 42) bits
are irrelevant to the operation of each AD1849K in Control
Mode. In Control Mode, a Codec requires 64 SCLK cycles to
be fully programmed. Additional SCLK cycles (more than 64)
that occur before the end of the frame will be ignored.
Codec would receive TSIN every 256 bits. In this case, Codec
#2's input Control Word will be positioned between Bit 64 and
Bit 127 in the input frame.
Control Word received as a serial input on the SDRX pin as a
serial output in the next frame on the SDTX pin. (SDTX will
be enabled regardless of the setting of the TXDIS bit, Control
Word Bit 40.) This echoing of the control information allows
the external controller to confirm that the Codec has received
the intended Control Word. For the four Codec daisy chain
example above, the Control Word will be echoed bit for bit as
an output between Bit 64 and Bit 127 in the next output frame.
In general, in Control Mode, the location of the echo Control
Word within a frame will be at the same word location as the
input Control Word.
Control Word that reflects the control register values operative
during the most recent Data Mode operation. If Control Mode
was entered prior to any Data Mode operation, this first output
word will simply reflect the standard default settings. DCB will
always be "1" in the first output echoed Control Word.
masters (i.e., the external controller and the Codec) and
guarantee unambiguous serial bus ownership. This software
handshake protocol for Control Mode to Data Mode transitions
makes use of the Data/Control Bit (DCB) in the Control Mode
Control Word (Bit 58). Prior to initiating the change to Control
Mode, the external controller should gradually attenuate the
audio outputs. The DCB handshake protocol requires the
from the external controller to the Codec may be "0" or "1" at
this point in the handshake.
ating as the master in the preceding Data Mode, immediately
three-stated immediately after D/
periods after D/
after it drives D/
operating as the master in the preceding Data Mode, the Codec
will three-state FSYNC, SDTX, and SCLK immediately after
start driving SCLK immediately.
master in the preceding Data Mode, the external controller
must continue to supply SCLK to the slave Codec for at least
three (3) SCLK periods after D/
externally until the first Control Word in Control Mode is
supplied by the external controller. This prevents false starts
and can be easily accomplished by using a pull-down resistor on
TSIN as recommended. The slave Codec drives TSOUT and
SDTX LO, then three-states SDTX, all within 1 1/2 (one and
one half) SCLK periods after D/
master in the preceding Data Mode, the external controller
must continue to supply SCLK to the slave Codec. A Control
Mode TSIN should be issued to the Codec three or more
SCLK periods after D/
defaults identified above, which among other actions, mutes all
When the external controller is ready to continue with the DCB
handshake, the Control Word sent by the external controller
should have the DCB reset to "0" along with arbitrary control
information (i.e., the control information does not have to be
valid, although if it is valid, it allows the external controller to
verify that the echoed Control Word is correct). The external
controller should continue to transmit this bit pattern with
to "0" (i.e., it must poll DCB until a "0" is read). This is the
first interlock of the DCB handshake.
was received on SDRX if a sample rate has been consistently
selected AND the clock source is generated using the internal
oscillator. Otherwise DCB = "0" will be echoed on SDTX in
the frame after at least 2 ms of consistent sample rate selection
expires. If SCLK or CLKIN is used as the clock source, the user
must guarantee that the source selection and sample rate are
stable for 2 ms before D/
external controller must take care not to set (or glitch) DCB =
"1" until after the echoed DCB = "0" has been received from
After it sees the DCB = "0" (and has optionally verified that the
echoed Control Word is correct), and when it is ready to
continue with the DCB handshake, the external controller
should transmit the desired and valid control information, but
now with DCB set to "1." The external controller can then
transmit arbitrary control information until the echoed DCB
from the Codec is also set to "l" (i.e., it must poll DCB until a
"l" is read). After this Control Word with DCB = "1," all future
control information received by the Codec during Control
Mode (i.e., while D/
received on SDRX if a sample rate has been consistently
selected AND the clock source is generated using the internal
oscillator. Otherwise DCB = "1" will be echoed on SDTX once
one sample rate selection has been held constant for at least
2 ms. If SCLK or CLKIN is used as the clock source, the user
must guarantee that the source selection and sample rate are
stable for 2 ms before D/
three-state the SDTX pin. The external controller must
continue to supply SCLK to the Codec until all 64 bits of the
Control Word with DCB = "1" have been transmitted by the
Codec, plus at least one  more SCLK after this 64-bit
Control Word (i.e., at least 65 SCLKs). Note that echoing the
full 64-bit Control Word makes the AD1849K match the
behavior of the CS4215.
Control mode DCB handshake is now complete. The Codec
will remain inactive until D/
consistently selected throughout the handshake, the AD1849K
and the CS4215 DCB protocols are equivalent.
in accordance with the SCLK, FSYNC, TSIN, and TSOUT
signals as shown in Figure 6. If the Codec enters Data Mode as
a master, it will generate one complete SCLK period before it
drives FSYNC HI; FSYNC will go HI with the second rising
edge of SCLK. This allows external devices driven by SCLK to
AD1849K Codec enters Data Mode as a slave, it can recognize
a TSIN LO-to-HI transition even if SCLK is simultaneously
making its first LO-to-HI transition. In fact, the AD1849K
serial interface will operate properly even if D/
sequence, including the DCB handshake.
minimum of external circuitry. The recommended circuits are
shown in Figures 11 through 20 and summarized in Figure 21.
Analog Devices estimates that the total cost of all the compo-
nents shown in these Figures, including crystals, to be less than
$5 in 10,000 piece quantities.
centered around analog ground. (For other audio equipment,
"line level" is much more loosely defined.) The AD1849K
SoundPort is a +5 V only powered device. Line level voltage
swings for the AD1849K are defined to be 1 V rms for ADC
input and 0.707 V rms for DAC output. Thus, 2 V rms input
analog signals must be attenuated and either centered around
the reference voltage intermediate between 0 V and + 5 V or
ac-coupled. The CMOUT pin will be at this intermediate
voltage, nominally 2.25 V. It has limited drive but can be used
as a voltage datum to an op amp input. Note, however, that
dc-coupled inputs are not recommended, as they provide no
performance benefits with the AD1849K architecture. Further-
more, dc offset differences between multiple dc-coupled inputs
create the potential for "clicks" when changing the input mux
Note that this is approximately a divide-by-two resistive divider.
are already at the 1 V rms levels expected by the AD1849K, the
resistors in parallel with the 560 pF capacitors should be
omitted and the series 5.1 k
to accommodate condenser microphones. Particular system
requirements will depend upon the characteristics of the
intended microphone. Figure 12 illustrates one example of how
an electret condenser mike requiring phantom power could be
connected to the AD1849K. CMOUT is shown buffered by an
op amp; a transistor like a 2N4124 will also work fine for this
purpose. Note that if a battery-powered microphone is used, the
buffer and R2s are not needed. The values of R1, R2, and C
should be chosen in light of the mic characteristics and intended
gain. Typical values for these might be R1 = 20 k
to center the output signals around analog ground. If dc-
coupling is desired, CMOUT could be used with op amps as
supplied by +5 V operational amps. The circuit shown ac
couples the headphones to the line output.
biased up to the CMOUT voltage, nominally 2.25 V. The
AD1849K allows for 6 dB larger output voltage swings by
resetting the OLB bit (Bit 59 of the Control Word) to "0."
Figure 15 illustrates an alternative headphone connection for
the AD1849K which uses the LOUT1C pin to eliminate the
need for ac coupling. The 12
LOUT1L, LOUT1R and LOUT1C are short-circuit protected.
Note that driving headphones directly as shown in Figure 15
with OLB = 0 will cause clipping for large input signals and will
only work with very efficient "Walkman-type" headphones. For
high quality headphone listening, Analog Devices recommends
the circuit shown in Figure 14 with OLB = 1.
from the AD1849K's mono outputs as shown in Figure 16.
Note that this output is differential. Analog Devices guarantees
specified distortion performance for speaker impedances of 48
cost of some distortion. When driving speakers much less than
close to Pin 21 as possible (especially the 0.1
The AD1849K must use 1.0
should be fundamental-mode and parallel-tuned. Two sources for
the exact crystals specified are Component Marketing Services
in Massachusetts, U.S. at 617-762-4339 and Cardinal Compo-
nents in New Jersey, U.S. at 201-746-0333. Note that using the
exact data sheet frequencies is not required and that external
oscillators. (See the description of the MCK1:0 control bits
above.) If using an external clock source, apply it to the crystal
input pins while leaving the crystal output pins unconnected.
Attention should be paid to providing low jitter external input
power-supply decoupling. Decoupling capacitors should be
placed as close as possible to package pins. If a separate analog
power supply is not available, we recommend the circuit shown
in Figure 20 for using a single +5 V supply. Ferrite beads suffice
for the inductors shown. This circuitry should be as close to the
supply pins as is practical.
outputs. Analog Devices also recommends pull-down resistors
for SCLK, FSYNC, SDTX, SDRX, and TSIN to provide
margin against system noise. CLKIN, CIN1, and CIN2, if not
used, should be grounded. A typical connection diagram is
shown in Figure 21, which serves to summarize the preceding
Figure 22. The analog plane and the digital plane are connected
directly under the AD1849K. Splitting the ground plane directly
under the SoundPort Codec is optimal because analog pins will
be located above the analog ground plane and digital pins will
be located directly above the digital ground plane for the best
isolation. The digital ground and analog grounds should be tied
together in the vicinity of the AD1849K. Other schemes may
also yield satisfactory results.
SoundPort Codec to four of Analog Devices' Fixed-Point
outputs for D/
flag output, it alone does require additional circuitry to generate
supplied with the AD1849K Evaluation Board. Source and
object codes arc available from your Analog Devices Sales
Representative or on the Analog Devices DSP Bulletin Board.
The DSP Bulletin Board telephone number is (617) 461-4258,
8 data bits, no parity, 1 stop bit, 300 to 2400 baud.
must be significantly more complicated than these three
examples because the C25's serial port cannot be a master,
which is required of the external controller during Control
compatible with the CS4215. These chips were independently
codeveloped to a common specification provided by Sun
Microsystems, Inc. Because of their independent development,
they will differ in performance and in minor details. A board can
be designed to accommodate either chip by attending to a few
differences in their required support circuitry.
during Control Mode, the AD1849K DCB handshake is
compatible with the CS4215. See text for more details.
to complete its internal input filter as shown in Figure 18.
The CS4215 calls the two pins on the AD1849K for these
capacitor connections, "no connects." By laying out a board
with these capacitors, either chip will work.
shown in Figure 11. In contrast, the recommended input
circuit for the CS4215 is a single-pole active filter requiring a
dual op amp. Though overkill for the AD1849K, this input
circuit will work with the AD1849K as well.
filters on analog outputs. As shown in Figure 13, the
AD1849K only requires ac coupling capacitors and resistors
for line-level dc bias. In contrast, the CS4215 has a single-
pole passive filter for its recommended line-level output
circuit. Though overkill for the AD1849K, this output circuit
will work with the AD1849K as well.
as a digital power supply. On the CS4215, this pin is a "no
connect." We strongly recommend connecting this pin to the
digital supply. Both chips should operate in this configura-
tion. Pin 39 (PLCC) and Pin 33 (TQFP) on the AD1849K is
used as a digital ground. On the CS4215, this pin is a "no
connect." We strongly recommend connecting this pin to the
digital ground plane. Both chips should operate in this
performance at low sample rates will be improved with the
Transition Band (Full-Scale Line-Level Inputs, 0 dB Gain)
(Full-Scale Inputs, 0 dB Attenuation)
Transition Band (Full-Scale Inputs, 0 dB Attenuation)
ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . 2
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AD1849K PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 7
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 8
Analog-to-Digital Datapath . . . . . . . . . . . . . . . . . . . . . . . 8
Digital-to-Analog Datapath . . . . . . . . . . . . . . . . . . . . . . . 8
Monitor Mix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Digital Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Supplies and Voltage Reference . . . . . . . . . . . . . . . 9
Autocalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Clocks and Sample Rates . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Mode Data and Control Registers . . . . . . . . . . . . . 14
Control Register Defaults . . . . . . . . . . . . . . . . . . . . . . . . 16
Clocks and the Serial Interface . . . . . . . . . . . . . . . . . . . . 17
Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Daisy-Chaining Multiple Codecs . . . . . . . . . . . . . . . . . . 19
Parallel I/O Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Control Word Echo . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DCB Handshaking Protocol . . . . . . . . . . . . . . . . . . . . . . 20
Control Mode to Data Mode Transition
CS4215 COMPATIBILITY . . . . . . . . . . . . . . . . . . . . . . . . 25
FREQUENCY RESPONSE PLOTS . . . . . . . . . . . . . . . . 26
PACKAGE--Outline Dimension Drawings . . . . . . . . . . . . 28