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Datasheet: 5962-8963701CA (Analog Devices)

High Precision, Wide-Band RMS-to-DC Converter

 

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Analog Devices
FUNCTIONAL BLOCK DIAGRAMS
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
High Precision,
Wide-Band RMS-to-DC Converter
AD637
The AD637 is available in two accuracy grades (J, K) for com-
mercial (0
°
C to +70
°
C) temperature range applications; two
accuracy grades (A, B) for industrial (­40
°
C to +85
°
C) applica-
tions; and one (S) rated over the ­55
°
C to +125
°
C temperature
range. All versions are available in hermetically-sealed, 14-lead
side-brazed ceramic DIPs as well as low cost cerdip packages. A
16-lead SOIC package is also available.
PRODUCT HIGHLIGHTS
1. The AD637 computes the true root-mean-square, mean
square, or absolute value of any complex ac (or ac plus dc)
input waveform and gives an equivalent dc output voltage.
The true rms value of a waveform is more useful than an
average rectified signal since it relates directly to the power of
the signal. The rms value of a statistical signal is also related
to the standard deviation of the signal.
2. The AD637 is laser wafer trimmed to achieve rated perfor-
mance without external trimming. The only external compo-
nent required is a capacitor which sets the averaging time
period. The value of this capacitor also determines low fre-
quency accuracy, ripple level and settling time.
3. The chip select feature of the AD637 permits the user to
power down the device down during periods of nonuse,
thereby, decreasing battery drain in remote or hand-held
applications.
4. The on-chip buffer amplifier can be used as either an input
buffer or in an active filter configuration. The filter can be
used to reduce the amount of ac ripple, thereby, increasing
the accuracy of the measurement.
PRODUCT DESCRIPTION
The AD637 is a complete high accuracy monolithic rms-to-dc
converter that computes the true rms value of any complex
waveform. It offers performance that is unprecedented in inte-
grated circuit rms-to-dc converters and comparable to discrete
and modular techniques in accuracy, bandwidth and dynamic
range. A crest factor compensation scheme in the AD637 per-
mits measurements of signals with crest factors of up to 10 with
less than 1% additional error. The circuit's wide bandwidth per-
mits the measurement of signals up to 600 kHz with inputs of
200 mV rms and up to 8 MHz when the input levels are above
1 V rms.
As with previous monolithic rms converters from Analog Devices,
the AD637 has an auxiliary dB output available to the user. The
logarithm of the rms output signal is brought out to a separate
pin allowing direct dB measurement with a useful range of
60 dB. An externally programmed reference current allows the
user to select the 0 dB reference voltage to correspond to any
level between 0.1 V and 2.0 V rms.
A chip select connection on the AD637 permits the user to
decrease the supply current from 2.2 mA to 350
µ
A during
periods when the rms function is not in use. This feature facili-
tates the addition of precision rms measurement to remote or
hand-held applications where minimum power consumption is
critical. In addition when the AD637 is powered down the out-
put goes to a high impedance state. This allows several AD637s
to be tied together to form a wide-band true rms multiplexer.
The input circuitry of the AD637 is protected from overload
voltages that are in excess of the supply levels. The inputs will
not be damaged by input signals if the supply voltages are lost.
FEATURES
High Accuracy
0.02% Max Nonlinearity, 0 V to 2 V RMS Input
0.10% Additional Error to Crest Factor of 3
Wide Bandwidth
8 MHz at 2 V RMS Input
600 kHz at 100 mV RMS
Computes:
True RMS
Square
Mean Square
Absolute Value
dB Output (60 dB Range)
Chip Select-Power Down Feature Allows:
Analog "3-State" Operation
Quiescent Current Reduction from 2.2 mA to 350
A
Side-Brazed DIP, Low Cost Cerdip and SOIC
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
BUFFER
AD637
ABSOLUTE
VALUE
SQUARER/DIVIDER
BIAS
SECTION
FILTER
25k
25k
1
2
3
4
5
6
7
14
13
12
11
10
9
8
16
15
SOIC (R) Package
BUFFER
AD637
ABSOLUTE
VALUE
SQUARER/DIVIDER
BIAS
SECTION
FILTER
25k
25k
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Ceramic DIP (D) and
Cerdip (Q) Packages
AD637­SPECIFICATIONS
(@ +25 C, and
15 V dc unless otherwise noted)
REV. E
­2­
AD637J/A
AD637K/B
AD637S
Model
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
TRANSFER FUNCTION
V
OUT
=
avg . (V
IN
)
2
V
OUT
=
avg . (V
IN
)
2
V
OUT
=
avg . (V
IN
)
2
CONVERSION ACCURACY
Total Error, Internal Trim
1
(Fig. 2)
1 0.5
0.5 0.2
1 0.5
mV
±
% of Reading
T
MIN
to T
MAX
3.0 0.6
2.0 0.3
6 0.7
mV
±
% of Reading
vs. Supply, + V
IN
= +300 mV
30
150
30
150
30
150
µ
V/V
vs. Supply, ­ V
IN
= ­300 mV
100
300
100
300
100
300
µ
V/V
DC Reversal Error at 2 V
0.25
0.1
0.25
% of Reading
Nonlinearity 2 V Full Scale
2
0.04
0.02
0.04
% of FSR
Nonlinearity 7 V Full Scale
0.05
0.05
0.05
% of FSR
Total Error, External Trim
±
0.5
±
0.1
±
0.25
±
0.05
±
0.5
±
0.1
mV
±
% of Reading
ERROR VS. CREST FACTOR
3
Crest Factor 1 to 2
Specified Accuracy
Specified Accuracy
Specified Accuracy
Crest Factor = 3
±
0.1
±
0.1
±
0.1
% of Reading
Crest Factor = 10
±
1.0
±
1.0
±
1.0
% of Reading
AVERAGING TIME CONSTANT
25
25
25
ms/
µ
F C
AV
INPUT CHARACTERISTICS
Signal Range,
±
15 V Supply
Continuous RMS Level
0 to 7
0 to 7
0 to 7
V rms
Peak Transient Input
±
15
±
15
±
15
V p-p
Signal Range,
±
5 V Supply
Continuous rms Level
0 to 4
0 to 4
0 to 4
V rms
Peak Transient Input
±
6
±
6
±
6
V p-p
Maximum Continuous Nondestructive
Input Level (All Supply Voltages)
±
15
±
15
±
15
V p-p
Input Resistance
6.4
8
9.6
6.4
8
9.6
6.4
8
9.6
k
Input Offset Voltage
±
0.5
±
0.2
±
0.5
mV
FREQUENCY RESPONSE
4
Bandwidth for 1% Additional Error (0.09 dB)
V
IN
= 20 mV
11
11
11
kHz
V
IN
= 200 mV
66
66
66
kHz
V
IN
= 2 V
200
200
200
kHz
±
3 dB Bandwidth
V
IN
= 20 mV
150
150
150
kHz
V
IN
= 200 mV
1
1
1
MHz
V
IN
= 2 V
8
8
8
MHz
OUTPUT CHARACTERISTICS
Offset Voltage
1
0.5
1
mV
vs. Temperature
±
0.05
0.089
±
0.04
0.056
±
0.04
0.07
mV/
°
C
Voltage Swing,
±
15 V Supply,
2 k
Load
0 to +12.0
+13.5
0 to +12.0
+13.5
0 to +12.0
+13.5
V
Voltage Swing,
±
3 V Supply,
2 k
Load
0 to +2
+2.2
0 to +2
+2.2
0 to +2
+2.2
V
Output Current
6
6
6
mA
Short Circuit Current
20
20
20
mA
Resistance, Chip Select "High"
0.5
0.5
0.5
Resistance, Chip Select "Low"
100
100
100
k
dB OUTPUT
Error, V
IN
7 mV to 7 V rms, 0 dB = 1 V rms
±
0.5
±
0.3
±
0.5
dB
Scale Factor
­3
­3
­3
mV/dB
Scale Factor Temperature Coefficient
+0.33
+0.33
+0.33
% of Reading/
°
C
­0.033
­0.033
­0.033
dB/
°
C
I
REF
for 0 dB = 1 V rms
5
20
80
5
20
80
5
20
80
µ
A
I
REF
Range
1
100
1
100
1
100
µ
A
BUFFER AMPLIFIER
Input Output Voltage Range
­V
S
to (+V
S
­V
S
to (+V
S
­V
S
to (+V
S
­ 2.5 V)
­ 2.5 V)
­ 2.5 V)
V
Input Offset Voltage
±
0.8
2
±
0.5
1
±
0.8
2
mV
Input Current
±
2
10
±
2
5
±
2
10
nA
Input Resistance
10
8
10
8
10
8
Output Current
(+5 mA,
(+5 mA,
(+5 mA,
­130
µ
A)
­130
µ
A)
­130
µ
A)
Short Circuit Current
20
20
20
mA
Small Signal Bandwidth
1
1
1
MHz
Slew Rate
5
5
5
5
V/
µ
s
DENOMINATOR INPUT
Input Range
0 to +10
0 to +10
0 to +10
V
Input Resistance
20
25
30
20
25
30
20
25
30
k
Offset Voltage
±
0.2
±
0.5
±
0.2
±
0.5
±
0.2
±
0.5
mV
CHIP SELECT PROVISION (CS)
RMS "ON" Level
Open or +2.4 V < V
C
< +V
S
Open or +2.4 V < V
C
< +V
S
Open or +2.4 V < V
C
< +V
S
RMS "OFF" Level
V
C
< +0.2 V
V
C
< +0.2 V
V
C
< +0.2 V
I
OUT
of Chip Select
CS "LOW"
10
10
10
µ
A
CS "HIGH"
Zero
Zero
Zero
On Time Constant
10
µ
s + ((25 k
)
×
C
AV
)
10
µ
s + ((25 k
)
×
C
AV
)
10
µ
s + ((25 k
)
×
C
AV
)
Off Time Constant
10
µ
s + ((25 k
)
×
C
AV
)
10
µ
s + ((25 k
)
×
C
AV
)
10
µ
s + ((25 k
)
×
C
AV
)
POWER SUPPLY
Operating Voltage Range
3.0
18
3.0
18
3.0
18
V
Quiescent Current
2.2
3
2.2
3
2.2
3
mA
Standby Current
350
450
350
450
350
450
µ
A
TRANSISTOR COUNT
107
107
107
NOTES
1
Accuracy specified 0-7 V rms dc with AD637 connected as shown in Figure 2.
2
Nonlinearity is defined as the maximum deviation from the straight line connecting the readings at 10 mV and 2 V.
3
Error vs. crest factor is specified as additional error for 1 V rms.
4
Input voltages are expressed in volts rms. % are in % of reading.
5
With external 2 k
pull down resistor tied to ­V
S
.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ABSOLUTE MAXIMUM RATINGS
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 V
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
18 V dc
Internal Quiescent Power Dissipation . . . . . . . . . . . . 108 mW
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . ­65
°
C to +150
°
C
Lead Temperature Range (Soldering 10 secs) . . . . . . . +300
°
C
Rated Operating Temperature Range
AD637J, K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
°
C to +70
°
C
AD637A, B . . . . . . . . . . . . . . . . . . . . . . . . ­40
°
C to +85
°
C
AD637S, 5962-8963701CA . . . . . . . . . . . ­55
°
C to +125
°
C
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
AD637AR
­ 40
°
C to +85
°
C
SOIC
R-16
AD637BR
­40
°
C to +85
°
C
SOIC
R-16
AD637AQ
­ 40
°
C to +85
°
C
Cerdip
Q-14
AD637BQ
­ 40
°
C to +85
°
C
Cerdip
Q-14
AD637JD
0
°
C to +70
°
C
Side Brazed Ceramic DIP D-14
AD637JD/+
0
°
C to +70
°
C
Side Brazed Ceramic DIP D-14
AD637KD
0
°
C to +70
°
C
Side Brazed Ceramic DIP D-14
AD637KD/+
0
°
C to +70
°
C
Side Brazed Ceramic DIP D-14
AD637JQ
0
°
C to +70
°
C
Cerdip
Q-14
AD637KQ
0
°
C to +70
°
C
Cerdip
Q-14
AD637JR
0
°
C to +70
°
C
SOIC
R-16
AD637JR-REEL
0
°
C to +70
°
C
SOIC
R-16
AD637JR-REEL7
0
°
C to +70
°
C
SOIC
R-16
AD637KR
0
°
C to +70
°
C
SOIC
R-16
AD637SD
­55
°
C to +125
°
C Side Brazed Ceramic DIP D-14
AD637SD/883B
­55
°
C to +125
°
C Side Brazed Ceramic DIP D-14
AD637SQ/883B
­55
°
C to +125
°
C Cerdip
Q-14
AD637SCHIPS
0
°
C to +70
°
C
Die
5962-8963701CA* ­55
°
C to +125
°
C Cerdip
Q-14
*A standard microcircuit drawing is available.
FILTER/AMPLIFIER
24k
24k
ONE QUADRANT
SQUARER/DIVIDER
BUFFER
AMPLIFIER
Q1
Q2
Q3
Q4
125
6k
6k
12k
24k
A5
A1
A2
ABSOLUTE VALUE VOLTAGE ­
CURRENT CONVERTER
I
1
I
3
I
4
A4
A3
BIAS
Q5
CAV
+V
S
RMS
OUT
COM
CS
DEN
INPUT
OUTPUT
OFFSET
dB
OUT
AD637
V
IN
BUFF OUT
BUFF IN
­V
S
Figure 1. Simplified Schematic
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD637 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD637
REV. E
­3­
WARNING!
ESD SENSITIVE DEVICE
AD637
REV. E
­4­
the AD637 can be ac coupled through the addition of a non-
polar capacitor in series with the input as shown in Figure 2.
BUFFER
AD637
ABSOLUTE
VALUE
SQUARER/DIVIDER
BIAS
SECTION
FILTER
25k
25k
1
2
3
4
5
6
7
14
13
12
11
10
9
8
C
AV
­V
S
+V
S
NC
V
IN
NC
OPTIONAL
AC COUPLING
CAPACITOR
V
O
=
V
IN
3
Figure 2. Standard RMS Connection
The performance of the AD637 is tolerant of minor variations in
the power supply voltages, however, if the supplies being used
exhibit a considerable amount of high frequency ripple it is
advisable to bypass both supplies to ground through a 0.1
µ
F
ceramic disc capacitor placed as close to the device as possible.
The output signal range of the AD637 is a function of the sup-
ply voltages, as shown in Figure 3. The output signal can be
used buffered or nonbuffered depending on the characteristics
of the load. If no buffer is needed, tie buffer input (Pin 1) to
common. The output of the AD637 is capable of driving 5 mA
into a 2 k
load without degrading the accuracy of the device.
SUPPLY VOLTAGE ­ DUAL SUPPLY ­ Volts
20
15
0
0
18
5
MAX V
OUT
­ Volts 2k
Load
10
10
5
15
3
Figure 3. AD637 Max V
OUT
vs. Supply Voltage
CHIP SELECT
The AD637 includes a chip select feature which allows the user
to decrease the quiescent current of the device from 2.2 mA to
350
µ
A. This is done by driving the CS, Pin 5, to below 0.2 V
dc. Under these conditions, the output will go into a high im-
pedance state. In addition to lowering power consumption, this
feature permits bussing the outputs of a number of AD637s to
form a wide bandwidth rms multiplexer. If the chip select is not
being used, Pin 5 should be tied high.
FUNCTIONAL DESCRIPTION
The AD637 embodies an implicit solution of the rms equation
that overcomes the inherent limitations of straightforward rms
computation. The actual computation performed by the AD637
follows the equation
V rms
=
Avg
V
IN
2
V rms


Figure 1 is a simplified schematic of the AD637, it is subdivided
into four major sections; absolute value circuit (active rectifier),
square/divider, filter circuit and buffer amplifier. The input volt-
age V
IN
which can be ac or dc is converted to a unipolar current
I1 by the active rectifier A1, A2. I1 drives one input of the
squarer divider which has the transfer function
I
4
=
I
1
2
I
3
The output current of the squarer/divider, I4 drives A4 which
forms a low-pass filter with the external averaging capacitor. If
the RC time constant of the filter is much greater than the long-
est period of the input signal than A4s output will be propor-
tional to the average of I4. The output of this filter amplifier is
used by A3 to provide the denominator current I3 which equals
Avg. I4 and is returned to the squarer/divider to complete the
implicit rms computation.
I
4
=
Avg
I
1
2
I
4
=
I
1
rms
and
V
OUT
= V
IN
rms
If the averaging capacitor is omitted, the AD637 will compute the
absolute value of the input signal. A nominal 5 pF capacitor should
be used to insure stability. The circuit operates identically to that of
the rms configuration except that I3 is now equal to I4 giving
I
4
=
I
1
2
I
4
I
4
=
I
1
The denominator current can also be supplied externally by pro-
viding a reference voltage, V
REF
, to Pin 6. The circuit operates
identically to the rms case except that I3 is now proportional to
V
REF
. Thus:
I
4
=
Avg
I
1
2
I
3
and
V
O
=
V
IN
2
V
DEN
This is the mean square of the input signal.
STANDARD CONNECTION
The AD637 is simple to connect for a majority of rms measure-
ments. In the standard rms connection shown in Figure 2, only
a single external capacitor is required to set the averaging time
constant. In this configuration, the AD637 will compute the
true rms of any input signal. An averaging error, the magnitude
of which will be dependent on the value of the averaging capaci-
tor, will be present at low frequencies. For example, if the filter
capacitor C
AV
, is 4
µ
F this error will be 0.1% at 10 Hz and in-
creases to 1% at 3 Hz. If it is desired to measure only ac signals,
REV. E
­5­
AD637
OPTIONAL TRIMS FOR HIGH ACCURACY
The AD637 includes provisions to allow the user to trim out
both output offset and scale factor errors. These trims will result
in significant reduction in the maximum total error as shown in
Figure 4. This remaining error is due to a nontrimmable input
offset in the absolute value circuit and the irreducible non-
linearity of the device.
The trimming procedure on the AD637 is as follows:
l. Ground the input signal, V
IN
and adjust R1 to give 0 V out-
put from Pin 9. Alternatively R1 can be adjusted to give the
correct output with the lowest expected value of V
IN
.
2. Connect the desired full scale input to V
IN
, using either a dc
or a calibrated ac signal, trim R3 to give the correct output at
Pin 9, i.e., 1 V dc should give l.000 V dc output. Of course, a
2 V peak-to-peak sine wave should give 0.707 V dc output.
Remaining errors are due to the nonlinearity.
INPUT LEVEL ­ Volts
5.0
2.5
5.0
0
2.0
0.5
ERROR ­ mV
1.0
0
2.5
1.5
AD637K MAX
INTERNAL TRIM
AD637K
EXTERNAL TRIM
AD637K: 0.5mV 0.2%
0.25mV 0.05%
EXTERNAL
Figure 4. Max Total Error vs. Input Level AD637K
Internal and External Trims
BUFFER
AD637
SQUARER/DIVIDER
BIAS
SECTION
FILTER
25k
25k
1
2
3
4
5
6
7
14
13
12
11
10
9
8
C
AV
­V
S
+V
S
V rms
OUT
R4
147
+
R3
1k
SCALE FACTOR ADJUST,
2%
R2
1M
R1
50k
­V
S
+V
S
V
IN
OUTPUT
OFFSET
ADJUST
ABSOLUTE
VALUE
Figure 5. Optional External Gain and Offset Trims
CHOOSING THE AVERAGING TIME CONSTANT
The AD637 will compute the true rms value of both dc and ac
input signals. At dc the output will track the absolute value of
the input exactly; with ac signals the AD637's output will ap-
proach the true rms value of the input. The deviation from the
ideal rms value is due to an averaging error. The averaging error
is comprised of an ac and dc component. Both components are
functions of input signal frequency f, and the averaging time
constant
(
: 25 ms/
µ
F of averaging capacitance). As shown in
Figure 6, the averaging error is defined as the peak value of the
ac component, ripple, plus the value of the dc error.
The peak value of the ac ripple component of the averaging er-
ror is defined approximately by the relationship:
50
6.3
f
in % of reading where (t > 1/f)
DC ERROR = AVERAGE OF OUTPUT­IDEAL
DOUBLE-FREQUENCY
RIPPLE
E
O
TIME
AVERAGE ERROR
IDEAL
E
O
Figure 6. Typical Output Waveform for a Sinusoidal Input
This ripple can add a significant amount of uncertainty to the
accuracy of the measurement being made. The uncertainty can
be significantly reduced through the use of a post filtering net-
work or by increasing the value of the averaging capacitor.
The dc error appears as a frequency dependent offset at the
output of the AD637 and follows the equation:
1
0.16
+
6.4
2
f
2
in % of reading
Since the averaging time constant, set by C
AV
, directly sets the
time that the rms converter "holds" the input signal during
computation, the magnitude of the dc error is determined only
by C
AV
and will not be affected by post filtering.
SINEWAVE INPUT FREQUENCY ­ Hz
100
0.1
1.0
10
10k
DC ERROR OR RIPPLE % OF READING
1k
100
10
DC ERROR
PEAK RIPPLE
Figure 7. Comparison of Percent DC Error to the Percent
Peak Ripple over Frequency Using the AD637 in the Stan-
dard RMS Connection with a 1
×
µ
F C
AV
The ac ripple component of averaging error can be greatly
reduced by increasing the value of the averaging capacitor.
There are two major disadvantages to this: first, the value of the
averaging capacitor will become extremely large and second, the
settling time of the AD637 increases in direct proportion to the
value of the averaging capacitor (Ts = 115 ms/
µ
F of averaging
capacitance). A preferable method of reducing the ripple is
through the use of the post filter network, shown in Figure 8.
This network can be used in either a one or two pole configura-
tion. For most applications the single pole filter will give the
best overall compromise between ripple and settling time.
AD637
REV. E
­6­
BUFFER
AD637
SQUARER/DIVIDER
BIAS
SECTION
FILTER
25k
25k
1
2
3
4
5
6
7
14
13
12
11
10
9
8
C
AV
­V
S
+V
S
+
ABSOLUTE
VALUE
RMS
OUTPUT
BUFFER
OUTPUT
ANALOG COM
OUTPUT
OFFSET
+
C2
R
X
24k
BUFFER INPUT
NC
CHIP
SELECT
DENOMINATOR
INPUT
dB
24k
FOR 1 POLE
FILTER, SHORT
R
X
AND
REMOVE C3
SIGNAL
INPUT
+
C3
NC
Figure 8. Two Pole Sallen-Key Filter
Figure 9a shows values of C
AV
and the corresponding averaging
error as a function of sine-wave frequency for the standard rms
connection. The 1% settling time is shown on the right side of
the graph.
Figure 9b shows the relationship between averaging error, signal
frequency settling time and averaging capacitor value. This
graph is drawn for filter capacitor values of 3.3 times the averag-
ing capacitor value. This ratio sets the magnitude of the ac and
dc errors equal at 50 Hz. As an example, by using a 1
µ
F averag-
ing capacitor and a 3.3
µ
F filter capacitor, the ripple for a 60 Hz
input signal will be reduced from 5.3% of reading using the
averaging capacitor alone to 0.15% using the single pole filter.
This gives a factor of thirty reduction in ripple and yet the set-
tling time would only increase by a factor of three. The values of
C
AV
and C2, the filter capacitor, can be calculated for the desired
value of averaging error and settling time by using Figure 9b.
The symmetry of the input signal also has an effect on the mag-
nitude of the averaging error. Table I gives practical component
values for various types of 60 Hz input signals. These capacitor
values can be directly scaled for frequencies other than 60 Hz,
i.e., for 30 Hz double these values, for 120 Hz they are halved.
For applications that are extremely sensitive to ripple, the two pole
configuration is suggested. This configuration will minimize
capacitor values and settling time while maximizing performance.
Figure 9c can be used to determine the required value of C
AV
,
C2 and C3 for the desired level of ripple and settling time.
INPUT FREQUENCY ­ Hz
100
0.01
1
100k
10
REQUIRED C
AV
­
F
100
1k
10k
10
1.0
0.1
VALUES FOR C
AV
AND
1% SETTLING TIME
FOR STATED % OF READING
AVERAGING ERROR*
ACCURACY 2% DUE TO
COMPONENT TOLERANCE
* %dc ERROR + %RIPPLE (Peak)
10% ERROR
1% ERROR
0.1% ERROR
0.01% ERROR
FOR 1% SETTLING TIME IN SECONDS
MULTIPLY READING BY 0.115
100
0.01
10
1.0
0.1
Figure 9a.
INPUT FREQUENCY ­ Hz
100
0.01
1
100k
10
REQUIRED C
AV
(AND C2)
C2 = 3.3
C
AV
100
1k
10k
10
1.0
0.1
5% ERROR
1% ERROR
0.1% ERROR
0.01% ERROR
VALUES OF C
AV
, C2 AND
1% SETTLING TIME FOR
STATED % OF READING
AVERAGING ERROR*
FOR 1 POLE POST FILTER
* %dc ERROR + % PEAK RIPPLE
ACCURACY 20% DUE TO
COMPONENT TOLERANCE
FOR 1% SETTLING TIME IN SECONDS
MULTIPLY READING BY 0.400
100
0.01
10
1.0
0.1
Figure 9b.
INPUT FREQUENCY ­ Hz
100
0.01
1
100k
10
REQUIRED C
AV
(AND C2 + C3)
C2 = C3 = 2.2
C
AV
100
1k
10k
10
1.0
0.1
5% ERROR
1% ERROR
0.1% ERROR
0.01% ERROR
VALUES OF C
AV
, C2 AND C3
AND 1% SETTLING TIME FOR
STATED % OF READING
AVERAGING ERROR*
2 POLL SALLEN-KEY FILTER
* %dc ERROR + % PEAK RIPPLE
ACCURACY 20% DUE TO
COMPONENT TOLERANCE
FOR 1% SETTLING TIME IN SECONDS
MULTIPLY READING BY 0.365
100
0.01
10
1.0
0.1
Figure 9c.
REV. E
­7­
AD637
Table I. Practical Values of C
AV
and C2 for Various Input
Waveforms
Input Waveform
and Period
Absolute Value
Circuit Waveform
and Period
Minimum
R C
AV
Time
Constant
Recommended C
AV
and C2
Values for 1% Averaging
Error@60Hz with T = 16.6ms
Recommended
Standard
Value C
AV
Recommended
Standard
Value C2
1%
Settling
Time
Symmetrical Sine Wave
Sine Wave with dc Offset
Pulse Train Waveform
1/2T
T
A
B
C
D
181ms
325ms
2.67sec
2.17sec
1.5 F
2.7 F
22 F
18 F
6.8 F
0.82 F
0.47 F
5.6 F
10(T ­ T
2
)
10(T ­ 2T
2
)
1/2T
T
2
T
2
T
2
T
2
0V
0V
0V
0V
T
T
T
T
T
T
T
FREQUENCY RESPONSE
The frequency response of the AD637 at various signal levels is
shown in Figure 10. The dashed lines show the upper frequency
limits for 1%, 10% and
±
3 dB of additional error. For example,
note that for 1% additional error with a 2 V rms input the high-
est frequency allowable is 200 kHz. A 200 mV signal can be
measured with 1% error at signal frequencies up to 100 kHz.
INPUT FREQUENCY ­ Hz
10
1k
10M
10k
V
OUT
­ Volts
100k
1M
1
0.1
0.01
1V RMS INPUT
2V RMS INPUT
7V RMS INPUT
100mV RMS INPUT
10mV RMS INPUT
1%
3dB
10%
Figure 10. Frequency Response
To take full advantage of the wide bandwidth of the AD637 care
must be taken in the selection of the input buffer amplifier. To
insure that the input signal is accurately presented to the con-
verter, the input buffer must have a ­3 dB bandwidth that is
wider than that of the AD637. A point that should not be over-
looked is the importance of slew rate in this application. For
example, the minimum slew rate required for a 1 V rms 5 MHz
sine-wave input signal is 44 V/
µ
s. The user is cautioned that this
is the minimum rising or falling slew rate and that care must be
exercised in the selection of the buffer amplifier as some amplifi-
ers exhibit a two-to-one difference between rising and falling slew
rates. The AD845 is recommended as a precision input buffer.
AC MEASUREMENT ACCURACY AND CREST FACTOR
Crest factor is often overlooked in determining the accuracy of
an ac measurement. Crest factor is defined as the ratio of the
peak signal amplitude to the rms value of the signal (C.F. = Vp/
V rms). Most common waveforms, such as sine and triangle
waves, have relatively low crest factors (
2). Waveforms which
resemble low duty cycle pulse trains, such as those occurring in
switching power supplies and SCR circuits, have high crest
factors. For example, a rectangular pulse train with a 1% duty
cycle has a crest factor of 10 (C.F. = 1
).
PULSEWIDTH ­ s
10
1.0
0.01
1
1000
10
INCREASE IN ERROR ­ %
100
0.1
CAV = 22 F
CF = 10
CF = 3
0
100 F
Vp
T
e
0
= DUTY CYCLE =
100 s
T
CF = 1/
e
IN
(rms) = 1 Volt rms
Figure 11. AD637 Error vs. Pulsewidth Rectangular Pulse
Figure 12 is a curve of additional reading error for the AD637
for a 1 volt rms input signal with crest factors from 1 to 11. A
rectangular pulse train (pulsewidth 100
µ
s) was used for this test
since it is the worst-case waveform for rms measurement (all
CREST FACTOR
+1.5
0
­1.5
1
11
2
INCREASE IN ERROR ­ %
3
4
5
6
7
8
9
10
+1.0
+0.5
+0.5
­1.0
POSITIVE INPUT PULSE
C
AV
= 22 F
Figure 12. Additional Error vs. Crest Factor
AD637
REV. E
­8­
V
IN
­ V rms
2.0
1.8
0.0
2.0
0.5
1.0
1.5
1.2
0.6
0.4
0.2
1.6
1.4
0.8
1.0
MAGNITUDE OF ERROR ­ % OF rms LEVEL
CF = 10
CF = 7
CF = 3
Figure 13. Error vs. RMS Input Level for Three Common
Crest Factors
the energy is contained in the peaks). The duty cycle and peak
amplitude were varied to produce crest factors from l to 10
while maintaining a constant 1 volt rms input amplitude.
CONNECTION FOR dB OUTPUT
Another feature of the AD637 is the logarithmic or decibel out-
put. The internal circuit which computes dB works well over a
60 dB range. The connection for dB measurement is shown in
Figure 14. The user selects the 0 dB level by setting R1 for the
proper 0 dB reference current (which is set to exactly cancel the
log output current from the squarer/divider circuit at the desired
0 dB point). The external op amp is used to provide a more
convenient scale and to allow compensation of the +0.33%/
°
C
temperature drift of the dB circuit. The special T.C. resistor R3
is available from Tel Labs in Londenderry, New Hampshire
(model Q-81) and from Precision Resistor Inc., Hillside, N.J.
(model PT146).
DB CALIBRATION
1. Set V
IN
= 1.00 V dc or 1.00 V rms
2. Adjust R1 for 0 dB out = 0.00 V
3. Set V
IN
= 0.1 V dc or 0.10 V rms
4. Adjust R2 for dB out = ­ 2.00 V
Any other dB reference can be used by setting V
IN
and R1
accordingly.
LOW FREQUENCY MEASUREMENTS
If the frequencies of the signals to be measured are below
10 Hz, the value of the averaging capacitor required to deliver
even 1% averaging error in the standard rms connection be-
comes extremely large. The circuit shown in Figure 15 shows an
alternative method of obtaining low frequency rms measure-
ments. The averaging time constant is determined by the prod-
uct of R and C
AV1
, in this circuit 0.5 s/
µ
F of C
AV
. This circuit
permits a 20:1 reduction in the value of the averaging capacitor,
permitting the use of high quality tantalum capacitors. It is
suggested that the two pole Sallen-Key filter shown in the dia-
gram be used to obtain a low ripple level and minimize the value
of the averaging capacitor.
If the frequency of interest is below 1 Hz, or if the value of the
averaging capacitor is still too large, the 20:1 ratio can be
increased. This is accomplished by increasing the value of R. If
this is done it is suggested that a low input current, low offset
voltage amplifier like the AD548 be used instead of the internal
buffer amplifier. This is necessary to minimize the offset error
introduced by the combination of amplifier input currents and
the larger resistance.
AD707JN
­V
S
+V
S
dB SCALE
FACTOR
ADJUST
R2
COMPENSATED
dB OUTPUT
+ 100mV/dB
5k
33.2k
R3
60.4
1k
*
BUFFER
AD637
SQUARER/DIVIDER
BIAS
SECTION
FILTER
25k
25k
1
2
3
4
5
6
7
14
13
12
11
10
9
8
C
AV
­V
S
+V
S
+
ABSOLUTE
VALUE
BUFFER
OUTPUT
ANALOG COM
OUTPUT
OFFSET
BUFFER INPUT
NC
CHIP
SELECT
DENOMINATOR
INPUT
dB
SIGNAL
INPUT
NC
1 F
SIGNAL
INPUT
RMS OUTPUT
+V
S
AD508J
+2.5 VOLTS
R1
500k
0dB ADJUST
10k
*1k + 3500ppm
TC RESISTOR TEL LAB Q81
PRECISION RESISTOR PT146
OR EQUIVALENT
Figure 14. dB Connection
REV. E
­9­
AD637
VECTOR SUMMATION
Vector summation can be accomplished through the use of two
AD637s as shown in Figure 16. Here the averaging capacitors
are omitted (nominal 100 pF capacitors are used to insure
stability of the filter amplifier), and the outputs are summed as
shown. The output of the circuit is
V
O
=
V
X
2
+
V
Y
2
This concept can be expanded to include additional terms by
feeding the signal from Pin 9 of each additional AD637 through
a 10 k
resistor to the summing junction of the AD711, and ty-
ing all of the denominator inputs (Pin 6) together.
If C
AV
is added to IC1 in this configuration, the output is
V
X
2
+
V
Y
2
. If the averaging capacitor is included on both
IC1 and IC2, the output will be
V
X
2
+
V
Y
2
.
This circuit has a dynamic range of 10 V to 10 mV and is lim-
ited only by the 0.5 mV offset voltage of the AD637. The useful
bandwidth is 100 kHz.
BUFFER
AD637
SQUARER/DIVIDER
BIAS
SECTION
FILTER
25k
25k
1
2
3
4
5
6
7
14
13
12
11
10
9
8
C
AV
­V
S
+V
S
+
ABSOLUTE
VALUE
NC
SIGNAL
INPUT
NC
100 F
AD548JN
­V
S
+V
S
FILTERED
V rms OUTPUT
1 F
1 F
1000pF
6.8M
NOTE: VALUES CHOSEN TO GIVE 0.1%
AVERAGING ERROR @ 1Hz
1M
50k
­V
S
+V
S
OUTPUT
OFFSET
ADJUST
C
AV1
3.3 F
499k
1%
R
3.3M
3.3M
V
IN
2
V rms
Figure 15. AD637 as a Low Frequency RMS Converter
BUFFER
AD637
SQUARER/DIVIDER
BIAS
SECTION
FILTER
25k
25k
1
2
3
4
5
6
7
14
13
12
11
10
9
8
­V
S
+V
S
ABSOLUTE
VALUE
100pF
V
X
IN
BUFFER
AD637
SQUARER/DIVIDER
BIAS
SECTION
FILTER
25k
25k
1
2
3
4
5
6
7
14
13
12
11
10
9
8
­V
S
+V
S
ABSOLUTE
VALUE
100pF
V
X
IN
V
OUT
=
V
X
2
+ V
V
2
5pF
10k
AD711K
EXPANDABLE
10k
10k
20k
Figure 16. AD637 Vector Sum Configuration
AD637
REV. E
­10­
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
TO-116 Package
(D-14)
14
1
7
8
0.098 (2.49) MAX
0.310 (7.87)
0.220 (5.59)
0.005 (0.13) MIN
PIN 1
0.100
(2.54)
BSC
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.070 (1.78)
0.030 (0.76)
0.150
(3.81)
MAX
0.785 (19.94) MAX
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
Cerdip Package
(Q-14)
14
1
7
8
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN
0.098 (2.49) MAX
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.200 (5.08)
MAX
0.785 (19.94) MAX
0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
15°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SOIC Package
(R-16)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.050 (1.27)
BSC
16
9
8
1
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
0.4133 (10.50)
0.3977 (10.00)
0.0125 (0.32)
0.0091 (0.23)
8
0
0.0291 (0.74)
0.0098 (0.25)
45
0.0500 (1.27)
0.0157 (0.40)
C804f­0­12/99 (rev. E)
PRINTED IN U.S.A.
© 2018 • ICSheet
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