reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
2 s ADC with Track/Hold
1 s DAC with Output Amplifier
AD7669, Dual DAC Output
Fast Bus Interface
Single or Dual 5 V Supplies
on a single monolithic chip. The AD7569 contains a high speed
successive approximation ADC with 2
fier with 1
ADC and the DAC. The AD7669 is similar, but contains two
DACs with output buffer amplifiers.
ply voltage of +5 V, input and output ranges of zero to 1.25 V
and zero to 2.5 volts may be programmed using the RANGE in-
put pin. Using a
processor control lines. Bus interface timing is extremely fast, al-
lowing easy connection to all popular 8-bit microprocessors. A
separate start convert line controls the track/hold and ADC to
give precise control of the sampling period.
logic. The AD7569 is packaged in a 24-pin, 0.3" wide "skinny"
DIP, a 24-terminal SOIC and 28-terminal PLCC and LCCC
packages. The AD7669 is available in a 28-pin, 0.6" plastic
DIP, 28-terminal SOIC and 28-terminal PLCC package.
interface a microprocessor to the analog world. No external
components or user trims are required and the overall accu-
racy of the system is tightly specified, eliminating the need
to calculate error budgets from individual component
the AD7569/AD7669 is specified for ac parameters, includ-
ing signal-to-noise ratio, distortion and input bandwidth.
with all modern microprocessors, with bus access and relin-
quish times less than 75 ns and write pulse width less than
J, A Versions
J, A Versions
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7569/AD7669 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
a short to AGND or V
of the device at these or any other condition above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
The term DAC (Digital-to-Analog Converter) throughout the
data sheet applies equally to the dual DACs in the AD7669 as
well as to the single DAC of the AD7569 unless otherwise
stated. It follows that the term V
Total Unadjusted Error
cludes internal voltage reference error, relative accuracy, gain
and offset errors.
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after al-
lowing for offset and gain errors. For the bipolar output ranges,
the endpoints of the DAC transfer function are defined as those
voltages that correspond to negative full-scale and positive full-
scale codes. For the unipolar output ranges, the endpoints are
code 1 and code 255. Code 1 is chosen because the amplifier is
now working in single supply and, in cases where the true offset
of the amplifier is negative, it cannot be seen at code 0. If the
relative accuracy were calculated between code 0 and code 255,
the "negative offset" would appear as a linearity error. If the off-
set is negative and less than 1 LSB, it will appear at code 1, and
hence the true linearity of the converter is seen between code 1
and code 255.
transition points from a straight line drawn between the end-
points of the ADC transfer function. For the bipolar input
ranges, these points are the measured, negative, full-scale transi-
tion point and the measured, positive, full-scale transition point.
For the unipolar ranges, the straight line is drawn between the
measured first LSB transition point and the measured full-scale
change and an ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of
ential nonlinearity of
mum step size or code width is 3/4 LSB.
analog output when the digital inputs change state with the
DAC selected. It is normally specified as the area of the glitch in
nV secs and is measured when the digital input code is changed
by 1 LSB at the major carry transition.
the analog output from the digital inputs, but is measured when
the DAC is not selected. It is essentially feedthrough across the
die and package. It is also a measure of the glitch impulse trans-
ferred to the analog output when data is read from the internal
ADC. It is specified in nV secs and is measured with WR high
and a digital code change from all 0s to all 1s.
an update at the output of the second DAC. The figure given is
the worst case and is expressed in nV secs. It is measured with
an update voltage of full scale.
wave from the output of one DAC, which appears at the output
of the second DAC (loaded with all 1s). The figure given is the
worst case for the second DAC output and is expressed as a ra-
tio in dBs. It is measured with a digitized sine wave (f
the output of the converter. The signal is the rms magnitude of
the fundamental. Noise is the rms sum of all the nonfundamen-
tal signals (excluding dc) up to half the sampling frequency.
SNR is dependent on the number of quantization levels used in
the digitization process; the more levels, the smaller the quanti-
zation noise. The theoretical SNR for a sine wave is given by
SNR = 50 dB.
the fundamental. For the AD7569/AD7669, Total Harmonic
Distortion (THD) is defined as
fb, any active device with nonlinearities will create distortion
products, of order (m + n), at sum and difference frequencies of
the second order terms include (fa + fb) and (fa fb) and the
third order terms include (2fa + fb), (2fa fb), (fa + 2fb) and
ground return paths are provided for the
DAC(s) and ADC to minimize crosstalk.
age ranges can be achieved (see Table I).
ply or 0 V for single supply). This pin is also
used with the RANGE pin to select the differ-
ent input/output ranges and changes the data
format from binary (V
the analog input voltage of the ADC and the
output voltage from the DAC(s).
chronous system reset that clears the DAC
register(s) to all 0s and clears the INT line of
the ADC (i.e., makes the ADC ready for new
conversion). In unipolar operation, this input
sets the output voltage to 0 V; in bipolar
operation, it sets the output to negative full
conjunction with CS to write data into the
AD7569 DAC register. It is used in conjunc-
tion with CS and A/B to write data into the
selected DAC register of the AD7669. Data is
transferred on the rising edge of WR.
selected when this input is active.
be active to access data from the part. In the
Mode 2 interface, RD going low starts con-
version. It is used in conjunction with the CS
input (see Digital Interface Section).
used when precise sampling is required. The
falling edge of ST starts conversion and drives
this pin is active, the ADC is performing a
conversion. The input signal is held prior to
the falling edge of BUSY (see Digital Inter-
ing low indicates that the conversion is com-
plete. INT goes high on the rising edge of CS
or RD and is also set high by a low pulse on
of CS and WR. With this input low, data is
written to the DACA register; with this input
high, data is written to the DACB register.
to determine the ADC conversion time. Inter-
nal clock operation is achieved by connecting
a resistor and capacitor to ground.
lected (see Table I).
that uses eight equally weighted current sources switched into
an R-2R ladder network to give a direct but unbuffered 0 V to
+1.25 V output range. The AD7669 is similar, but contains two
D/A converters. The current sources are fabricated using PNP
transistors. These transistors allow current sources that are
driven from positive voltage logic and give a zero-based output
range. The output voltage from the voltage switching R-2R lad-
der network has the same positive polarity as the reference;
therefore, the D/A converter can be operated from a single
power supply rail.
bandgap reference and a control amplifier. The current sources
are switched to either the ladder or AGND
tling time for the output voltage of the DAC. The R-2R ladder
network of the DAC consists of highly stable, thin-film resistors.
A simplified circuit diagram for the D/A converter section is
shown in Figure 3. An identical D/A converter is used as part of
the A/D converter, which is discussed later.
noninverting op amp. This op amp is capable of developing
unipolar output ranges, or from dual supplies (
work that provides four voltage ranges at the output of the op
amp. The output voltage range is determined by the RANGE
0 V to +2.5 V,
to the input voltage range of the A/D converter.
in typically less than 500 ns. Operating the part from single or
dual supplies has no effect on the positive-going settling time.
However, the negative-going output settling time to voltages
near 0 V in single supply will be slightly longer than the settling
time to negative full scale for dual supply operation. Addition-
ally, to ensure that the output voltage can go to 0 V in single
with output voltages near 0 V with V
age nears 0 V in single supply. In dual supply operation the full
sink capability of 1.25 mA is maintained over the entire output
mances of the amplifier are essentially identical. The output
noise from the amplifier, with full scale on the DAC, is 200
the amplifier is shown in the typical performance graphs.
that provides a low noise, temperature compensated reference
voltage for both the DAC and the ADC. The reference is
trimmed for absolute accuracy and temperature coefficient. The
bandgap reference is generated with respect to V
ADC reference. This can be seen in the DAC ladder network
configuration in Figure 3.
between the external bus and DAC data inputs and ADC data
outputs. The threshold levels of all digital inputs and outputs
are compatible with either TTL or 5 V CMOS levels. Internal
input protection of all digital pins is achieved by on-chip distrib-
plies to the digital inputs of the DAC and the digital outputs of
the successive approximation technique to achieve a fast conver-
sion time of 2
conversion has been started, another conversion start should not
be attempted until the conversion in progress is completed.
Exercising the RESET input does not affect conversion; the
the end of the previous conversion. The INT line does not have
to be cleared at the end of conversion. The ADC will continue
to convert correctly, but the function of the INT line will be
The analog input voltage, V
proximately 50 ns after the second falling edge of the input
CLK following a conversion start. If t
as the first falling clock edge. If t
cycle later. The succeeding bit decisions are made approxi-
mately 50 ns after a CLK edge until conversion is complete.
source charging the external capacitor (C
ing and the CLK pin goes to the DGND potential. Connections
AD7569/AD7669. Due to process variations, the actual operat-
ing frequency for this R
DAC Timing and Control--AD7569
AD7569. The part contains an 8-bit DAC register, which is
loaded from the data bus under control of CS and WR. The
data contained in the DAC register determines the analog out-
put from the DAC. The WR input is an edge-triggered input,
and data is transferred into the DAC register on the rising edge
of WR. Holding CS and WR low does not make the DAC regis-
low pulse on the RESET line, and for the unipolar output ranges,
the output remains at 0 V after RESET returns high. For the bi-
polar output ranges, a low pulse on RESET causes the output to
go to negative full scale.
put and is also useful when used as a zero override in system cali-
bration cycles. If the RESET input is connected to the system
the output latch, and the SAR is reset in readiness for a new
conversion. A single conversion lasts for 8 input clock cycles.
track-and-hold amplifier. To accommodate different full-scale
ranges, the analog input signal is conditioned by a gain/offset
network that conditions all input ranges so the internal ADC al-
ways works with a 0 V to +1.25 V signal. As a result, the input
current on the V
AD7569/AD7669 allows the ADC to accurately convert an in-
put sine wave of 2.5 V peak-to-peak amplitude up to a fre-
quency of 200 kHz, the Nyquist frequency of the ADC when
operated at its maximum throughput rate of 400 kHz. This
maximum rate of conversion includes conversion time and time
between conversions. Because the input bandwidth of the T/H
amplifier is much larger than 200 kHz, the input signal should
be band-limited to avoid converting high-frequency noise
the user. The T/H amplifier goes from its tracking mode to its
hold mode at the start of conversion. This occurs when the
ADC receives a conversion start command from either ST or
or with an externally applied clock. When using an external
clock, the CLK input of the AD7569/AD7669 may be driven
directly from 74HC, 4000B series buffers (such as 4049) or
from TTL buffers. When conversion is complete, the internal
clock is disabled. The external clock can continue to run be-
tween conversions without being disabled. The mark/space ratio
of the external clock can vary from 70/30 to 30/70.
AD7569 DAC; the write cycle timing diagram is shown in
the AD7669. The part contains two 8-bit DAC registers that are
loaded from the data bus under the control of CS, A/B and WR.
Address line A/B selects which DAC register the data is
loaded to. The data contained in the DAC registers determines
the analog output from the respective DACs. The WR input is
an edge-triggered input, and data is transferred into the selected
DAC register on the rising edge of WR. Holding CS and WR
low does not make the selected DAC register transparent. The
low pulse on the RESET line, and for the unipolar output
ranges, the outputs remain at 0 V after RESET returns high.
For the bipolar output ranges, a low pulse on RESET causes the
outputs to go to negative full scale. In unipolar applications, the
override in system calibration cycles. If the RESET input is con-
nected to the system RESET line, then the DAC outputs reset
to 0 V when the entire system is reset. Figure 9 shows the DAC
input control logic for the AD7669, and the write cycle timing
diagram is shown in Figure 8.
ating modes. In the first mode, the ST line is used to start con-
version and drive the track-and-hold into hold mode. At the end
of conversion, the track-and-hold returns to its tracking mode.
The second mode is achieved by hard-wiring the ST line high.
In this case, CS and RD start conversion, and the microproces-
sor is driven into a WAIT state for the duration of conversion by
The timing diagram for the first mode is shown in Figure 10. It
can be used in digital signal processing and other applications
where precise sampling in time is required. In these applica-
tions, it is important that the signal sampling occurs at exactly
equal intervals to minimize errors due to sampling uncertainty
or jitter. In these cases, the ST line is driven by a timer or some
precise clock source.
AD7569/AD7669 track-and-hold amplifier into its hold mode.
to its tracking mode on this rising edge of BUSY. The INT line
can be used to interrupt the microprocessor. A READ to the
AD7569/AD7669 address accesses the data, and the INT line is
reset on the rising edge of CS or RD. Alternatively, the INT can
be used to trigger a pulse that drives the CS and RD and places
the data into a FIFO or buffer memory. The microprocessor can
then read a batch of data from the FIFO or buffer memory at
some convenient time. The ST input should not be high when
(ST pulse) is asynchronous to the microprocessor, that a READ
does not occur during a conversion. Trying to read data from
the device during a conversion can cause errors to the conver-
sion in progress. Also, pulsing the ST line a second time before
conversion ends should be avoided since it too can cause errors
in the conversion result. In applications where precise sampling
is not critical, the ST pulse can be generated from a micropro-
cessor WR or RD line gated with a decoded address (different
from AD7569/AD7669 CS address).
ber of input channels are required to be converted by the ADC.
Figure 11 shows the circuit configuration for such an applica-
tion. The signal that drives the ST input of the AD7569/
AD7669 is also used to drive the ENABLE input of the multi-
plexer. The multiplexer is enabled on the rising edge of the ST
pulse while the input signal is held on the falling edge; therefore,
the signal must have settled to within 8 bits over the duration of
this ST pulse. The settling time, including t
thus determines the width of the ST pulse. This is suited to ap-
plications where a number of input channels needs to be succes-
sively sampled or scanned.
cessors, which can be forced into a WAIT state for at least 2
achieve this mode. The microprocessor starts a conversion and
is halted until the result of the conversion is read from the con-
verter. Conversion is initiated by executing a memory READ to
the AD7569/AD7669 address, bringing CS and RD low. BUSY
subsequently goes low (forcing the microprocessor READY or
WAIT input low), placing the microprocessor into a WAIT
state. The input signal is held on the falling edge of RD (assum-
ing CS is already low or is coincident with RD). When the con-
version is complete (BUSY goes high), the processor completes
the memory READ and acquires the newly converted data.
While conversion is in progress, the ADC places old data (from
the previous conversion) on the data bus. The timing diagram
for this interface is shown in Figure 12.
processor to start conversion, WAIT, and then READ data with
a single READ instruction. The user does not have to worry
about servicing interrupts or ensuring that software delays are
long enough to avoid reading during conversion. The fast con-
version time of the ADC ensures that for many microprocessors,
the processor is not placed in a WAIT state for an excessive
amount of time.
voice recognition, echo cancellation and adaptive filtering, the
dynamic characteristics (SNR, Harmonic Distortion, Intermod-
ulation Distortion) of both the ADC and DAC are critical. The
AD7569/AD7669 is specified dynamically as well as with stan-
dard dc specifications. Because the track/hold amplifier has a
wide bandwidth, an antialiasing filter should be placed on the
sine-wave signal of very low distortion to the V
(FFT) plot or Histogram plot is then generated from which SNR,
harmonic distortion and dynamic differential nonlinearity data
can be obtained. For the DAC, the codes for an ideal sine wave
are stored in PROM and loaded down to the DAC. The output
spectrum is analyzed, using a spectrum analyzer to evaluate SNR
taken, it is possible to plot a histogram showing the frequency of
occurrence of each of the 256 ADC codes. If a particular step is
wider than the ideal 1 LSB width, the code associated with that
step will accumulate more counts than for the code for an ideal
step. Likewise, a step narrower than ideal width will have fewer
counts. Missing codes are easily seen because a missing code
means zero counts for a particular code. The absence of large
spikes in the plot indicates small differential nonlinearity.
small differential nonlinearity and no missing codes for an input
frequency of 204 kHz. For a sine-wave input, a perfect ADC
would produce a cusp probability density function described by
probability of occurrence at a voltage V.
are shown in the Typical Performance Graphs section of the data
modulation distortion, an input (either to V
put signal of 130 kHz. The SNR is 48.4 dB. It can be seen that
most of the harmonics are buried in the noise floor. It should be
noted that the harmonics are taken into account when calculat-
ing the SNR. The relationship between SNR and resolution (N)
is expressed by the following equation:
errors. These errors will cause a degradation in SNR. By work-
ing backward from the above equation, it is possible to get a
measure of ADC performance expressed in effective number of
bits (N). This effective number of bits is plotted versus fre-
quency in Figure 14. The effective number of bits typically falls
between 7.7 and 7.8, corresponding to SNR figures of 48.1 dB
and 48.7 dB.
trum from the DAC with an ideal sine-wave table loaded to the
data inputs of the DAC. In this case, the SNR is 46 dB.
ADSP-2100. The ADC is in the Mode 2 interface mode, which
means that the ADSP-2100 is halted during conversion. This is
achieved using the decoded address output. This is gated with
processor and allows it to finish off the READ instruction.
(125 ns cycle), the DMWR pulse also has to be stretched also
for write cycles. This is achieved using the 74121, which gener-
ates a pulse that is fed back to DMACK. The duration of this
pulse determines how long the ADSP-2100 write cycle is
stretched. The buffers driving the DMACK line must have
open-collector outputs. Writing data to the relevant AD7569/
AD7669 DAC is achieved using a single instruction, <DM
(addr) = MRO>, where addr is the decoded address of that
DAC, and MRO contains the data to be loaded to the DAC reg-
ister. Data is read from the ADC also, using a single instruction
<MRO = DM (addr)>, where the conversion result is placed in
the MRO data register.
put/output port for the IBM PC. Figure 20 shows an interface
that realizes this function. The ADC is configured in the Mode
1 interface mode, and conversions are initiated using a precise
clock source for equidistant sampling intervals. At the end of
conversion, the INT line goes low, and the 74121 generates
The ADC is configured for operation in the Mode 1 interface
mode. A precise timer or clock source starts conversion in appli-
cations requiring equidistant sampling intervals. The scheme
used, whereby INT of the AD7569/AD7669 generates an inter-
rupt on the Z80, is limited in that it does not allow the ADC to
be sampled at the maximum rate. This is because the time be-
tween samples has to be long enough to allow the Z80 to service
its interrupt and read data from the ADC. To overcome this,
some buffer memory or FIFO could be placed between the
AD7569/AD7669 and the Z80. Writing data to the relevant
AD7569/AD7669 DAC simply consists of a <LD (nn), A> in-
struction where nn is the decoded address for that DAC. Read-
ing data from the ADC, after an INT has been received,
consists of a < LDA, (nn)> instruction.
case, the ADC is configured in the Mode 2 interface mode. This
means that the one read instruction starts conversion and reads
the data. The read cycle is stretched out over the entire conver-
sion period by taking the INT line back into the DTACK input
of the 68008. The additional gates are required so the 68008
receives a DTACK when the processor is writing data to the
AD7569/AD7669. In this case, there are no wait states intro-
duced into the write cycle. Writing data to the relevant AD7569/
AD7669 DAC consists of a <MOVE.B Dn, addr> where Dn is
the data register, which contains the data to be loaded to that
DAC, and addr is the decoded address for the DAC. Data is
read from the ADC using a <MOVE.B addr,Dn> with the con-
version result placed in register Dn.
data from the ADC and places the conversion result into a regis-
ter on the 74646. The rising edge of this pulse generates an in-
terrupt request to the processor. The conversion result is read
from the 74646 register by performing an I/O read to the
decoded address of the 74646. Writing data to the relevant
AD7569/AD7669 DAC involves an I/O write to the 74646,
which transfers the data to the data inputs of the AD7569/
AD7669. Data is latched into the selected DAC register on the
rising edge of IOW.
several output voltage ranges. The part can produce unipolar
output ranges of 0 V to +1.25 V or 0 V to +2.5 V and bipolar
output ranges of 1.25 V to +1.25 V or 2.5 V to +2.5 V. Con-
nections for these various output ranges are outlined below.
of 0 V to +1.25 V. This is achieved by tying the V
configuration of the AD7669 gives the same output range. The
table for output voltage versus the digital code in the DAC regis-
ter is shown in Table IV.
RANGE input to AGND
operation is approximately 1 V. When the part is configured
for bipolar outputs, the input coding becomes twos comple-
ment. The table for output voltage versus the digital code in the
DAC register is shown in Table V. Note as with the unipolar
configuration, a digital input code of all 0s produces an output
of 0 V. It should be noted, however, that a low pulse on the
the RANGE input to V
voltage versus digital code is as in Table V with 2.V
four input ranges as the output ranges on the DAC. Whatever
output range is selected for the DAC also applies to the input
range of the ADC.
minimize crosstalk, writing data to the DAC while the ADC is
performing a conversion may result in an incorrect conversion
from the ADC due to an interaction of currents between the
DAC and ADC. Therefore, to ensure correct operation of the
ADC, the DAC register should not be updated while the ADC
an input and output range of 0 V to +1.25 V (the AD7669 con-
figuration is similar). The nominal transfer characteristic for this
range is shown in Figure 22. The output code is Natural Binary
with 1 LSB = (1.25/256)V = 4.88 mV.
in this case, 1 LSB = (2.5/256)V = 9.76 mV.
(0 V to +1.25 V) Operation
for bipolar inputs when V
function for bipolar (1.25 V to +1.25 V) operation. The LSB
size for this range is (2.5/256)V = 9.76 mV.
to that of Figure 23, but now FS = 5 V and the LSB size is
(5/256)V = 19.5 mV.
full-scale error have little or no effect on system performance. A
(1.25 V to +1.25 V) Operation
quantized by the ADC, digitally processed and recreated using
the DAC. In these types of applications, the offset error can be
eliminated by ac coupling the recreated signal. Full-scale error
effect is linear and does not cause problems as long as the input
signal is within the full dynamic range of the ADC. An impor-
tant parameter in DSP applications is Differential Nonlinearity,
and this is not affected by either offset or full-scale error.
set and full-scale error can be adjusted to zero. Figure 24 shows
the additional components required for offset and full-scale er-
ror adjustment. Offset error must be adjusted before full-scale
error. Zero offset is achieved by adjusting the offset of the op
amp driving V
and adjust the op amp offset voltage until the ADC output code
flickers between 0000 0000 and 0000 0001. For zero full-scale
error, apply an analog input of FS 3/2 LSBs and adjust R1 un-
til the ADC output code flickers between 1111 1110 and 1111
1/2 LSB at the analog input and adjust the op amp offset volt-
age until the output code flickers between 1111 1111 and 0000
0000. For zero full-scale error, apply +FS/2 3/2 LSB at the
analog input and adjust R1 until the ADC output code flickers
between 0111 1110 and 0111 1111.
error between the desired position and the actual position to be
monitored and corrected. The correction is achieved by adjust-
ing the ratio of the phase currents in the motor windings until
the required head position is reached.
technique with its on-chip dual DACs for positioning the disk
drive head, and onboard ADC for monitoring the position of the
head. A generalized circuit for a closed-loop microstepping sys-
tem is shown in Figure 26. The DAC waveforms are shown in
Figure 27, along with the direction information for clockwise ro-
tation supplied by the controller.
tion. This allows the circuit of Figure 26 to be completely uni-
polar (+5 V, +12 V supplies); no negative power supplies are
required. The power output stage is a dual H-Bridge device
such as the UDN-2998W from Sprague Electric. The phase
currents in both windings are detected by means of the small
value sense resistors, R
compared with the respective DAC output voltage. The com-
parators in turn chop the phase winding current. The ADC
completes the feedback path by converting information from a
suitable transducer for analysis by the controller.
which is useful in such applications as monitoring flow rates,
temperature, pressure, etc. The circuit ensures that a peak will
not be missed while at the same time does not require the mi-
croprocessor to frequently monitor the data. The peak value is
stored in the A/D converter and can be read at any time.
put. When the input signal exceeds the current stored value, the
output of the TL311 goes low, triggering the Q output of the
74121. This low-going pulse starts a conversion on the AD7569
ADC, and at the end of conversion latches the result into the
DAC. This pulse must be at least 120 ns greater than the con-
version time of the ADC. The Q output is used to drive the
strobe input of the TL311, resetting the TL311 output high in
readiness for another conversion.
data to be read by the microprocessor while at the same time
ensuring that the DAC is not updated when the microprocessor
reads the data. It may be necessary to monitor the AD7569
pulse width from the processor must be less than 1
(both floppy and hard disk) that allows higher positional resolu-
tion of the disk drive head over that obtainable from a full- step
driven stepper motor. Typically, a two-phase stepper motor has
its phase currents driven with a sine-cosine relationship. These
cosinusoidal signals are generated by two DACs driven with the
appropriate data. The resolution of the DACs determines the
number of microsteps into which each full step can be divided.
For example, with a 1.8
tion possible in any control application; however, the positional
accuracy can be significantly worse than that offered by the
original full-step accuracy specification due to load torque effects.
to use a closed-loop system where the position of the disk drive
and Direction Signals for Clockwise Rotation with the
to provide a delay on the input signal. The circuit of Figure 28
shows how a simple analog delay line can be implemented,
based on the AD7569. The input signal is sampled using the
AD7569 ADC, and converted data is loaded into the 6116 (2K
ing one of the output lines of the HCT4040 counter to reset the
coun-ter. This can be done using a simple switch in a manual
system or by a multiplexer in a programmable delay application.
Data is written to the DAC using the inverted input clock signal.
set). From this point forward, the delayed data is read from the
6116 and loaded to the DAC before the newly converted data is
written into the same memory location. The input clock to the
system can be a square wave of maximum input frequency 200
frequency if required. The clock low time has to be equal to the
conversion time and access time of the ADC plus the setup time
required for the 6116. The clock high time has only to be equal
to the setup time for the DAC plus the delay time through the
counter and the access time of the 6116.
determines the maximum possible delay. Using the HCT4040,
and the 6116 with an input clock frequency of 200 kHz, the
maximum delay is 5 ms on a maximum input frequency of
100 kHz. Using 64K memory, with an 8 kHz input clock fre-
quency, the maximum delay is 8 seconds on a maximum input
frequency of 4 kHz.
recorder. In this case, transients on the input signal are con-
verted and stored in memory. The transient can then be recalled
from memory at a later time, and the transient waveform can be
recreated using the AD7569 DAC.
sample-and-hold function. Basically, the ADC samples and con-
verts the input signal into an 8-bit digital word. The 8 bits of
data are then loaded to the DAC and the sampled value is re-
stored to analog form. The sampled value is held until the DAC
register is updated. The full-scale matching between the ADC
and the DAC on the AD7569 ensures a typical error of less than
1% between the analog input voltage and the "held" output
voltage. Figure 29 shows the connections required on the
AD7569 to achieve this infinite sample-and-hold function.
sis of a circuit to provide a tare function for a weigh scale sys-
tem. Figure 30 shows a circuit for a weigh scale system. It
incorporates a tare function using a simple circuit based on the
reference to supply the low impedance load cell transducer. The
load cell output is amplified by the AD624 precision instrumen-
tation amplifier with gain adjustment provided by R1. The out-
put of the AD624 is applied to the noninverting input of a unity
gain differential summing amplifier that uses the AD707, a high
precision op amp with low drift. The AD707 feeds a 3 1/2 digit
The input signal to the panel meter is also applied to the analog
input of the AD7569 for the tare function. When the tare switch
(S1) is closed, a tare cycle commences and V
to zero. Thus, the tare function is used to give a readout of zero
for any undesired weight, such as a box, when only the item
placed in it is to be weighed. The tare function can also be used
in calibrating the system, to cancel out offset errors due to the
load cell, AD624 and differential amplifier.
such as: simple, low cost circuit--no need for microprocessor,
software, etc.--and low power consumption.