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Datasheet: 5962-8853801PA (Analog Devices)

Dual Precision JFET-Input Operational Amplifier

 

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Analog Devices
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
OP215
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
Dual Precision JFET-Input
Operational Amplifier
FEATURES
High Slew Rate: 10 V/ s Min
Fast Settling Time: 0.9 s to 0.1% Type
Low Input Offset Voltage Drift: 10 V/ C Max
Wide Bandwidth: 3.5 MHz Min
Temperature-Compensated Input Bias Currents
Guaranteed Input Bias Current: 18 nA Max (125 C)
Bias Current Specified Warmed Up over Temperature
Low Input Noise Current: 0.01 pA/
÷
Hz Type
High Common-Mode Rejection Ratio 86 dB Min
Pin Compatible with Standard Dual Pinouts
Models with MIL-STD-883 Class B Processing Available
GENERAL DESCRIPTION
The OP215 offers the proven JFET-input performance advantages
of high speed and low input bias current with the tracking and
convenience advantages of a dual op amp configuration.
Low input offset voltages, low input currents, and low drift are
featured in these high-speed amplifiers.
On-chip zener-zap trimming is used to achieve low V
OS,
while a
bias-current compensation scheme gives a low input bias current
V+
NOMINV
INPUT+
J3
J1
Q5
R1
J2
C1
7.4
pF
J4
Q12
­INV
INPUT
Q8
R3
Q6
J5
J11
Q7
NULL
R8
J8 J7
R7
NULL
Q1
Q3
R9
Q11
R4
R5
3.6
k
Q16
Q13
Q15
R6
3.6k
Q14
Q4
Q2
R2
C2
7.4pF
Q10
Q9
J6
Q19
Q17
Q18
Q21
J9
Q20
J10
Q23
R13
Q24
Q22
OUTPUT
R10
Q25
R11
R12
NOTE
R7, R8 ARE ELECTRONICALLY ADJUSTED
ON-CHIP FOR MINIMUM OFFSET VOLTAGE
Figure 1. Simplified Schematic (1/2 OP215)
at elevated temperature. Thus, the OP215 features an input bias
current of 1.4 nA at 70
C ambient (not junction) temperature
which greatly extends the application usefulness of this device.
Applications include high-speed amplifiers for current output
DACs, active filters, sample-and-hold buffers, and photocell
amplifiers. For additional precision JFET op amps, see the
OP249 and AD712 data sheets.
REV. A
­2­
OP215­SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
OP215E
OP215G
Parameter
Symbol
Conditions
Min
Type
Max
Min
Type
Max
Unit
Input Offset Voltage
V
OS
R
S
= 50
W
0.2
1.0
2.0
4.0
mV
`G' Grade
2.5
6.0
mV
Input Offset Current
1
I
OS
T
j
= 25
C
3
50
3
100
pA
Device Operating
5
100
5
200
pA
Input Bias Current
1
I
B
T
j
= 25
C
±15
±100
±15
±300
pA
Device Operating
±18
±300
±18
±600
pA
Input Resistance
R
IN
10
1,2
10
1,2
W
Large-Signal Voltage
A
VO
R
L
2 k
W,
150
500
50
200
V/mV
Gain
V
O
=
±10 V
Output Voltage Swing
V
O
R
L
= 10 k
W
±12
±13
±12
±13
V
R
L
= 2 k
W
±11
±12.7
±11
±12.7
V
Supply Current
I
SY
6.0
8.5
7.0
10.0
mA
`G' Grade
7.0
12.0
mA
Slew Rate
SR
A
VCL
= 1
10
18
5
15
V/ s
Gain Bandwidth
GBW
3.5
5.7
3.0
5.4
MHz
Product
3
Closed-Loop Bandwidth CLBW
A
VCL
= 1
13
12
MHz
Setting Time
t
S
To 0.01%
2.3
2.4
s
To 0.05%
2
1.1
1.2
s
To 0.10%
0.9
1.0
s
Input Voltage Range
IVR
10.2
14.8
10.1
14.8
V
­10.2
­11.5
­10.1
­11.5
V
Common-Mode
CMRR
V
CM
=
±IVR
82
100
80
96
dB
Rejection Ratio
E, G Grades
Power Supply Rejection
PSRR
V
S
=
±10 V to ±16 V
10
51
V/V
Ratio
V
S
=
±10 V to ±15 V
16
100
V/V
Input Noise Voltage
n
f
O
= 100 Hz
20
20
nV/
÷Hz
Density
f
O
= 1,000 Hz
15
15
nV/
÷Hz
Input Noise Current
I
n
f
O
= 100 Hz
0.01
0.01
pA/
÷Hz
Density
f
O
= 1,000 Hz
0.01
0.01
pA/
÷Hz
Input Capacitance
C
IN
3
3
pF
NOTES
1
Input bias current is specified for two different conditions. The T
j
= 25
C specification is with the junction at ambient temperature; the device operating specification is
with the device operating in a warmed up condition at 25
C ambient. The warmed up bias-current value is correlated to the junction temperature value via the curves
of I
S
versus T
j
and I
S
versus T
A
. PMI has a bias-current compensation circuit that gives improved bias current and bias current over temperature versus standard
JFET input op amps. I
S
and I
OS
are measured at V
CM
= 0.
2
Setting time is defined here for a unity gain inverter connection using 2 k
W resistors. It is the time required for the error voltage (the voltage at the inverting input pin
on the amplifier) to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter. See setting time test circuit.
3
Sample tested.
Specifications are subject to change without notice.
(at V
S
=
±15 V, T
A
= 25 C, unless otherwise noted.)
REV. A
­3­
OP215
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
OP215E
OP215G
Parameter
Symbol
Conditions
Min
Type
Max
Min
Type
Max
Unit
Input Offset Voltage
V
OS
R
S
= 50
W
0.4
1.65
3.5
8.0
mV
Average Input Offset
Voltage Drift
Without External Trim
1
TCV
OS
3
15
6
V/
C
With External Trim
TCV
OSn
R
P
= 100 k
W
3
4
V/
C
Input Offset Current
2
I
OS
T
j
= 70
C
0.06
0.45
0.08
0.65
nA
T
A
= 70
C
0.08
0.80
0.10
1.2
nA
Device Operating
Input Bias Current
2
I
S
T
j
= 70
C
±0.12 ±0.70
±0.14 ±0.9
nA
T
A
= 70
C
±0.16 ±1.40
±0.19 ±1.8
nA
Device Operating
Input Voltage Range
IVR
10.2
14.7
10.1
14.7
V
­10.2
­11.4
­10.1
­11.3
V
Common-Mode
CMRR
V
CM
=
±IVR
80
98
76
94
dB
Rejection Ratio
Power Supply Rejection
PSRR
V
S
=
±10 V to ±16 V
13
100
Ratio
V
S
=
±10 V to ±15 V
20
159
V/V
Large-Signal
A
VO
R
L
2 k
W
50
180
35
130
V/mV
Voltage Gain
V
O
=
±10 V
Output Voltage Swing
V
O
R
L
10 k
W
±12
±13
±12
±13
V
NOTES
1
Sample tested.
2
Input bias current is specified for two different conditions. The T
j
= 25
C specification is with the junction at ambient temperature; the Device Operating specification is
with the device operating in a warmed up condition at 25
C ambient. The warmed up bias-current value is correlated to the junction temperature value via the curves
of I
S
versus T
j
and I
S
versus T
A
. PMI has a bias-current compensation circuit that gives improved bias current and bias current over temperature versus standard
JFET input op amps. I
S
and I
OS
are measured at V
CM
= 0.
Specifications are subject to change without notice.
(at V
S
=
±15 V, 0 C T
A
70 C for E Grade, ­40 C T
A
+85 C for G Grade, unless
otherwise noted.)
REV. A
OP215
­4­
ORDERING INFORMATION
1
Package
Temperature
T
A
= 25
C,
Model
Type
Range
V
OS
Max (mV)
OP215EZ
2
8-Lead CerDIP
COM
1.0
OP215GP
2
8-Lead Plastic DIP
XIND
6.0
For military processed devices, please refer to the standard microcircuit drawing
(SMD) available at www.dscc.dla.mil/programs/milspec/default.asp
SMD Part Number
ADI Equivalent
5962-8853801GA
2
OP215AJMDA
5962-8853801PA
OP215AZMDA
5962-8838032A
2
OP215BRCMDA
NOTES
1
Burn-in is available on commercial and industrial temperature range parts in CerDIP and plastic
DIP packages.
2
Not for new design, obsolete April 2002.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP215 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage
OP215E, OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . .
±18 V
Operating Temperature Range
OP215E . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0
C to +70C
OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . . ­40
C to +85C
Maximum Junction Temperature (T
j
) . . . . . . . . . . . . . . 150
C
Differential Input Voltage
OP215E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±40 V
OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±30 V
Input Voltage
2
OP215E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20 V
OP215G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±16 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . ­65
C to +150C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300
C
Junction Temperature (T
j
) . . . . . . . . . . . . . ­65
C to +150C
NOTES
1
Absolute maximum ratings apply to packaged parts, unless otherwise noted.
2
Unless otherwise specified, the absolute maximum negative input voltage is equal
to one volt more positive than the negative power supply voltage.
Package Type
JA
*
JC
Unit
8-Lead Hermetic DIP (Z)
134
12
C/W
8-Lead Plastic DIP (P)
96
37
C/W
*
JA
is specified for worst-case mounting conditions, i.e.,
JA
is specified for
device in socket for CerDIP and P-DIP packages.
PIN CONFIGURATION
8
7
6
5
1
2
3
4
V+
OUT B
­IN B
+IN B
OUT A
­IN A
+IN A
­ +
­
+
A
B
REV. A
­5­
Typical Performance Characteristics­OP215
10
0%
100
90
500ns
5V
TPC 1. Large-Signal Transient
Response
FREQUENCY ­ Hz
GAIN ­ dB
90
1M
10M
100M
16
14
12
10
8
6
4
2
0
­2
­4
­6
­8
­10
100
110
120
130
140
150
160
170
180
190
200
PHASE SHIFT ­ Degrees
18
PHASE MARGIN = 66
A
V
> 10
A
V
= 1
V
S
= 15V
T
A
= 25 C
TPC 4. Closed-Loop Bandwidth and
Phase Shift vs. Frequency
FREQUENCY ­ Hz
PEAK-T
O-PEAK AMPLITUDE ­
V
28
100K
24
20
16
12
8
4
0
1M
10M
V
S
= 15V
T
A
= 25 C
A
V
= 1
TPC 7. Maximum Output Swing vs.
Frequency
10
0%
100
90
100ns
20mV
TPC 2. Small-Signal Transient
Response
TEMPERATURE ­ C
B
AND
WIDTH ­ MHz
28
­50
V
S
= 15V
BANDWIDTH VARIATION FROM
5 < V
S
< 20V IS < 5%
CLOSED-LOOP
BANDWIDTH A
V
= 1
GAIN BANDWIDTH
PRODUCT
24
20
16
12
8
4
0
­25
0
25
50
75
100
125
TPC 5. Bandwidth vs. Temperature
AMBIENT TEMPERATURE ­ C
SLEW RA
TE ­
V/
s
70
­50
A
V
= 1
V
S
= 15V
NEGATIVE
60
50
40
30
20
10
0
­25
0
25
50
75
100
125
POSITIVE
TPC 8. Slew Rate vs. Temperature
SETTLING TIME ­ s
OUTPUT
V
O
L
T
A
GE SWING FR
OM 0V ­
V
10
0
5
0
­5
­10
0.5
1.0
1.5
2.0
2.5
V
S
= 15V
T
A
= 25 C
A
V
= ­1
10mV
5mV
1mV
10mV
5mV
1mV
TPC 3. Settling Time
FREQUENCY ­ Hz
OPEN-LOOP
V
O
L
T
A
GE GAIN ­ dB
120
1
80
60
40
20
0
-20
10
100
1k
10k 100k 1M 10M
100
100M
V
S
= 15V
T
A
= 25 C
TPC 6. Open-Loop Frequency
Response
FREQUENCY­ Hz
COMMON-MODE REJECTION RA
TIO ­ dB
100
1
80
60
40
20
0
10
100
1k
10k 100k 1M
10M 100M
V
S
= 15V
T
A
= 25 C
TPC 9. Common-Mode Rejection
Ratio vs. Frequency
REV. A
OP215
­6­
BASIC CONNECTIONS
2k 0.1%
+15V
­15V
5k
0.1%
SCOPE
2k
2N4416
5k 0.1%
SUMMING
MODE
2k 0.1%
2
3
OP215
A
100pF
3k
A
V
= ­1
+15V
V
OUT
2N4416
0
10V
4
8
1
Figure 2. Settling Time Test Circuit
OP215
A
+15V
8
4
­15V
2k
100pF
V
OUT
1
V
IN
2
3
+5V
­5V
0V
Figure 3. Slew Rate Test Circuit
FREQUENCY ­ Hz
PO
WER SUPPL
Y REJECTION ­ dB
120
10
110
100
90
80
70
60
50
40
30
20
10
0
100
1k
10k
100k
1M
10M
T
A
= 25 C
NEGATIVE
SUPPLY
POSITIVE
SUPPLY
TPC 10. Power Supply Rejection vs.
Frequency
FREQUENCY ­ Hz
OUTPUT IMPED
ANCE ­
100
1k
10
1
0.1
10k
100k
1M
10M
V
S
=
15V
T
A
= 25 C
A
V
= 100
A
V
= 10
A
V
= 1
TPC 11. Output Impedance vs.
Frequency
FREQUENCY ­ Hz
VO
LTA
GE NOISE DENSITY ­ nV/

Hz
140
1
120
100
80
60
40
20
0
10
100
1k
10k
V
S
= 15V
T
S
= 25 C
1/f CORNER
FREQUENCY
TPC 12. Voltage Noise Density vs.
Frequency
OP215
A
OUT A
V+
­IN
+IN
Rp
100k
NOTE
V
OS
CAN BE TRIMMED WITH POTENTIOMETERS RANGING FROM
10 k TO 1 M . FOR MOST UNITS TCV
OS
WILL BE MINIMUM WHEN
V
OS
IS ADJUSTED WITH A 100k POTENTIOMETER.
Figure 4. Input Offset Voltage Nulling
REV. A
OP215
­7­
BASIC CONNECTIONS
OP215
B
OP215
A
1
7
100k
200
100k
3
2
5
6
8
+15V
­15V
NOTES
1. T
A
= 125 C TO 150 C
2. RESISTORS ARE TYPE
RN55D, 1%
4
Figure 5. Burn-In Circuit
APPLICATIONS INFORMATION
Dynamic Operating Considerations
As with most amplifiers, care should be taken with lead dress,
component placement, and supply de-coupling in order to ensure
stability. For example, resistors from the output to an input should
be placed with the body close to the input to minimize "pick up"
and maximize the frequency of the feedback pole by minimizing
the capacitance from the input to ground.
A feedback pole is created when the feedback around any amplifier
is resistive. The parallel resistance and capacitance from the
input of the device (usually the inverting input) to ac ground
sets the frequency of the pole. In many instances, the frequency
of this pole is much greater than the expected 3 dB frequency of
the closed-loop gain and, consequently, there is negligible effect
on stability margin. However, if the feedback pole is less than
approximately six times the expected 3 dB frequency, a lead
capacitor should be placed from the output to the negative input
of the op amp. The value of the added capacitor should be such
that the RC time constant of this capacitor and the resistance it
parallels is greater than, or equal to, the original feedback pole
time constant.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead CERDIP
(Z-Suffix)
1
4
8
5
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13)
MIN
0.055 (1.4)
MAX
0.100 (2.54) BSC
15°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.405 (10.29) MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
8-Lead Plastic DIP
(P-Suffix)
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.022 (0.558)
0.014 (0.356)
0.160 (4.06)
0.115 (2.93)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
8
1
4
5
PIN 1
0.280 (7.11)
0.240 (6.10)
0.100 (2.54)
BSC
0.430 (10.92)
0.348 (8.84)
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.325 (8.25)
0.300 (7.62)
REV. A
­8­
C02683­0­4/02(A)
PRINTED IN U.S.A.
OP215
Revision History
Location
Page
Data Sheet changed from REV. 0 to REV. A.
Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3
Edits to ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to PACKAGE TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Deleted TYPICAL ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to BURN-IN CIRCUIT figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
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