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Datasheet: 5962-0053001HXA (Analog Devices)

Dual Channel, 12-Bit, 80 MSPS A/D Converter with Analog Input Signal Conditioning

 

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Analog Devices

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REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD13280
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001
FEATURES
Dual, 80 MSPS Minimum Sample Rate
Channel-to-Channel Matching, 1% Gain Error
90 dB Channel-to-Channel Isolation
DC-Coupled Signal Conditioning
80 dB Spurious-Free Dynamic Range
Selectable Bipolar Inputs ( 1 V and 0.5 V Ranges)
Integral Single-Pole Low-Pass Nyquist Filter
Two's Complement Output Format
3.3 V Compatible Outputs
1.85 W per Channel
Industrial and Military Grade
APPLICATIONS
Radar Processing (Optimized for I/Q Baseband Operation)
Phased Array Receivers
Multichannel, Multimode Receivers
GPS Antijamming Receivers
Communications Receivers
Dual Channel, 12-Bit, 80 MSPS A/D Converter
with Analog Input Signal Conditioning
PRODUCT DESCRIPTION
The AD13280 is a complete dual channel signal processing
solution including on board amplifiers, references, ADCs, and
output termination components to provide optimized system
performance. The AD13280 has on-chip track-and-hold circuitry
and utilizes an innovative multipass architecture to achieve 12-bit,
80 MSPS performance. The AD13280 uses innovative high-
density circuit design and laser-trimmed thin-film resistor networks
to achieve exceptional channel matching, impedance control,
and performance while still maintaining excellent isolation,
and providing for significant board area savings.
Multiple options are provided for driving the analog input,
including single-ended, differential, and optional series filtering.
The AD13280 also offers the user a choice of analog input
signal ranges to further minimize additional external signal
conditioning, while still remaining general purpose.
The AD13280 operates with
5.0 V for the analog signal condi-
tioning with a separate 5.0 V supply for the analog-to-digital
conversion, and 3.3 V digital supply for the output stage. Each
channel is completely independent allowing operation with
independent encode and analog inputs, and maintaining mini-
mal crosstalk and interference.
The AD13280 is packaged in a 68-lead ceramic gull wing package.
Manufacturing is done on Analog Devices, Inc. MIL-38534
Qualified Manufacturers Line (QML) and components are
available up to Class-H (40
C to +85C). The components are
manufactured using Analog Devices, Inc. high-speed comple-
mentary bipolar process (XFCB).
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 80 MSPS.
2. Input signal conditioning included; gain and impedance match.
3. Single-ended, differential, or off-module filter options.
4. Fully tested/characterized full channel performance.
5. Compatible with 14-bit (up to) 65 MSPS family.
FUNCTIONAL BLOCK DIAGRAM
100 OUTPUT TERMINATORS
TIMING
3
9
12
VREF
DROUT
12
ENC
ENC
D9A
D10A D11A
(MSB)
D0B
(LSB)
D1B
D3B
D2B
D4B
D5B
D6B
D7B
D8B
TIMING
D9B
7
5
ENC
ENC
BIN
D10B
D11B (MSB)
(LSB) D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
AD13280
DROUTA
100 OUTPUT TERMINATORS
AMP-IN-B-2
AMP-IN-B-1
AMP-IN-A-2
AMP-IN-A-1
AMP-OUT-A
AIN
A+IN
B+IN
AMP-OUT-B
DROUTB
DROUT
VREF
REV. 0
2
AD13280SPECIFICATIONS
(AV
CC
= +5
V, AV
EE
= 5 V, DV
CC
= +3.3 V; applies to each ADC with Front-End
Amplifier unless otherwise noted.)
Test
Mil
AD13280AZ/BZ
Parameter
Temp
Level
Subgroup
Min
Typ
Max
Unit
RESOLUTION
12
Bits
DC ACCURACY
1
No Missing Codes
Full
IV
12
Guaranteed
Offset Error
25
C
I
1
2.2
1.0
+2.2
% FS
Full
VI
2, 3
2.2
1.0
+2.2
% FS
Offset Error Channel Match
Full
VI
1, 2, 3
1.0
0.1
+1.0
%
Gain Error
2
25
C
I
1
3
1.0
+1
% FS
Full
VI
2, 3
5.0
2.0
+5.0
% FS
Gain Error Channel Match
25
C
I
1
1.5
0.5
+1.5
%
Max
VI
2
3.0
1.0
+3.0
%
Min
VI
3
5
1.0
+5
%
SINGLE-ENDED ANALOG INPUT
Input Voltage Range
AMP-IN-X-1
Full
V
0.5
V
AMP-IN-X-2
Full
V
1.0
V
Input Resistance
AMP-IN-X-1
Full
IV
12
99
100
101
AMP-IN-X-2
Full
IV
12
198
200
202
Capacitance
25
C
V
4.0
7.0
pF
Analog Input Bandwidth
3
Full
V
100
MHz
DIFFERENTIAL ANALOG INPUT
Analog Signal Input Range
A+IN to AIN and B+IN to BIN
4
Full
V
1
V
Input Impedance
25
C
V
618
Analog Input Bandwidth
Full
V
50
MHz
ENCODE INPUT (ENC,
ENC)
1
Differential Input Voltage
Full
IV
12
0.4
V p-p
Differential Input Resistance
25
C
V
10
k
Differential Input Capacitance
25
C
V
2.5
pF
SWITCHING PERFORMANCE
Maximum Conversion Rate
5
Full
VI
4, 5, 6
80
MSPS
Minimum Conversion Rate
5
Full
IV
12
20
MSPS
Aperture Delay (t
A
)
25
C
V
1.5
ns
Aperture Delay Matching
25
C
IV
12
250
500
ps
Aperture Uncertainty (Jitter)
25
C
V
0.3
ps rms
ENCODE Pulsewidth High at Max Conversion Rate
25
C
IV
12
4.75
6.25
8
ns
ENCODE Pulsewidth Low at Max Conversion Rate
25
C
IV
12
4.75
6.25
8
ns
Output Delay (t
OD
)
Full
V
5
ns
Encode, Rising to Data Ready, Rising Delay
Full
V
8.5
ns
SNR
1, 6
Analog Input @ 10 MHz
25
C
I
4
67.5
70
dBFS
Min
II
6
64.5
dBFS
Max
II
5
67.5
dBFS
Analog Input @ 21 MHz
25
C
I
4
67.5
70
dBFS
Min
II
6
64
dBFS
Max
II
5
67.5
dBFS
Analog Input @ 37 MHz
25
C
I
4
63.5
65
dBFS
Min
II
6
61.5
dBFS
Max
II
5
63.5
dBFS
SINAD
1, 7
Analog Input @ 10 MHz
25
C
I
4
67
69
dBFS
Min
II
6
63.5
dBFS
Max
II
5
67
dBFS
Analog Input @ 21 MHz
25
C
I
4
65
68.5
dBFS
Min
II
6
63
dBFS
Max
II
5
65
dBFS
Analog Input @ 37 MHz
25
C
I
4
54.5
59
dBFS
Min
II
6
53
dBFS
Max
II
5
54.5
dBFS
REV. 0
3
AD13280
Test
Mil
AD13280AZ/BZ
Parameter
Temp
Level
Subgroup
Min
Typ
Max
Unit
SPURIOUS-FREE DYNAMIC RANGE
1, 8
Analog Input @ 10 MHz
25
C
I
4
75
80
dBFS
Min
II
6
70
Max
II
5
75
Analog Input @ 21 MHz
25
C
I
4
68
75
dBFS
Min
II
6
67
Max
II
5
68
Analog Input @ 37 MHz
25
C
I
4
56
62
dBFS
Min
II
6
55
Max
II
5
56
SINGLE-ENDED ANALOG INPUT
Passband Ripple to 10 MHz
25
C
V
0.05
dB
Passband Ripple to 25 MHz
25
C
V
0.1
dB
DIFFERENTIAL ANALOG INPUT
Passband Ripple to 10 MHz
25
C
V
0.3
dB
Passband Ripple to 25 MHz
25
C
V
0.82
dB
TWO-TONE IMD REJECTION
9
f
IN
= 9.1 MHz and 10.1 MHz
25
C
I
4
75
80
dBc
f
1
and f
2
are 7 dB
Min
II
6
71
Max
II
5
75
f
IN
= 19.1 MHz and 20.7 MHz
25
C
V
4
77
dBc
f
1
and f
2
are 7 dB
f
IN
= 36 MHz and 37 MHz
25
C
V
4
60
dBc
f
1
and f
2
are 7 dB
CHANNEL-TO-CHANNEL ISOLATION
10
25
C
IV
12
90
dB
TRANSIENT RESPONSE
25
C
V
25
ns
DIGITAL OUTPUTS
11
Logic Compatibility
CMOS
DVCC = 3.3 V
Logic "1" Voltage
Full
I
1, 2, 3
2.5
DVCC 0.2
V
Logic "0" Voltage
Full
I
1, 2, 3
0.2
0.5
V
DVCC = 5 V
Logic "1" Voltage
Full
V
DVCC 0.3
V
Logic "0" Voltage
Full
V
0.35
V
Output Coding
Two's Complement
POWER SUPPLY
AV
CC
Supply Voltage
12
Full
IV
4.85
5.0
5.25
V
I (AV
CC
) Current
Full
I
1, 2, 3
310
338
mA
AV
EE
Supply Voltage
12
Full
IV
5.25
5.0
4.75
V
I (AV
EE
) Current
Full
I
1, 2, 3
38
49
mA
DV
CC
Supply Voltage
12
Full
IV
3.135
3.3
3.465
V
I (DV
CC
) Current
Full
I
1, 2, 3
34
46
mA
I
CC
(Total) Supply Current per Channel
Full
I
1, 2, 3
369
433
mA
Power Dissipation (Total)
Full
I
1, 2, 3
3.72
4.05
W
Power Supply Rejection Ratio (PSRR)
Full
V
0.01
% FSR/% V
S
NOTES
1
All ac specifications tested by driving ENCODE and
ENCODE differentially. Single-ended input: AMP-IN-X-1 = 1 V p-p, AMP-IN-X-2 = GND.
2
Gain tests are performed on AMP-IN-X-1 input voltage range.
3
Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4
For differential input: +IN = 1 V p-p and IN = 1 V p-p (signals are 180
out of phase). For single-ended input: +IN = 2 V p-p and = IN = GND.
5
Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50%
5%.
6
Analog Input signal power at 1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 80 MSPS. SNR
is reported in dBFS, related back to converter full scale.
7
Analog Input signal power at 1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 80 MSPS. SINAD is
reported in dBFS, related back to converter full scale.
8
Analog Input signal at 1 dBFS; SFDR is ratio of converter full scale to worst spur.
9
Both input tones at 7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product.
10
Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B Channel.
11
Digital output logic levels: DV
CC
= 3.3 V, C
LOAD
= 10 pF. Capacitive loads > 10 pF will degrade performance.
12
Supply voltage recommended operating range. AV
CC
may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range
AV
CC
= 5.0 V to 5.25 V.
Specifications subject to change without notice.
REV. 0
AD13280
4
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD13280 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL
1
AV
CC
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V
AV
EE
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V to 0 V
DV
CC
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . V
EE
to
V
CC
Analog Input Current . . . . . . . . . . . . . . 10 mA to +10 mA
Digital Input Voltage (ENCODE) . . . . . . . . . . . . . 0 to V
CC
ENCODE,
ENCODE Differential Voltage . . . . . . . . 4 V max
Digital Output Current . . . . . . . . . . . . . . 10 mA to +10 mA
ENVIRONMENTAL
2
Operating Temperature (Case) . . . . . . . . . 40
C to +85C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 175
C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300
C
Storage Temperature Range (Ambient) . . 65
C to +150C
NOTES
1
Absolute maximum ratings are limiting values applied individually, and beyond
which the serviceability of the circuit may be impaired. Functional operability is not
necessarily implied. Exposure to absolute maximum rating conditions for an
extended period of time may affect device reliability.
2
Typical thermal impedance for "ES" package:
JC
2.2
C/W;
JA
24.3
C/W.
TEST LEVEL
I
100% Production Tested.
II 100% Production Tested at 25
C, and sample tested at
specified temperatures. AC testing done on sample basis.
III Sample Tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI 100% production tested with temperature at 25
C: sample
tested at temperature extremes.
PIN CONFIGURATION
68-Lead Ceramic Leaded Chip Carrier
(ES-68C)
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
21
27
43
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
9
61
8
7
6
5
68 67 66 65 64 63 62
4
3
2
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD13280
AGNDB
AV
EE
B
AV
CC
B
AGNDB
D10A
DROUTB
AGNDA
AV
EE
A
D0A(LSB)
D1A
D2A
D3A
D4A
D5A
AGNDB
ENCODEB
ENCODEB
DV
CC
B
D0B(LSB)
AGNDA
AGNDA
AMP-OUT-A
A+IN
A
IN
AGNDA
AMP-IN-A-2
AMP-IN-A-1
AGNDB
SHIELD
D1B
D2B
D3B
DGNDA
D11B(MSB)
D10B
D9B
DGNDB
AV
CC
A
AGNDB
B
IN
B+IN
AGNDB
AMP-IN-B-2
AMP-OUT-B
AMP-IN-B-1
D8B
D7B
D6B
D5B
D4B
DGNDB
NC
SHIELD
DROUTA
D11A(MSB)
D8A
D9A
D7A
D6A
DGNDA
ENCODEA
ENCODEA
AGNDA
AGNDA
DV
CC
A
NC
NC
NC = NO CONNECT
NC
ORDERING GUIDE
Model
Temperature Range (Case)
Package Description
Package Option
AD13280AZ
25
C to +85C
68-Lead Ceramic Leaded Chip Carrier
ES-68C
AD13280AF
25
C to +85C
68-Lead Ceramic Leaded Chip Carrier
ES-68C
with Nonconductive Tie-Bar
5962-0053001HXA
40
C to +85C
68-Lead Ceramic Leaded Chip Carrier
ES-68C
AD13280/PCB
25
C
Evaluation Board with AD13280AZ
REV. 0
AD13280
5
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Function
1, 35
SHIELD
Internal Ground Shield between Channels
2, 3, 9, 10, 13, 16
AGNDA
A Channel Analog Ground. A and B grounds should be connected as close to
the device as possible.
4
AIN
Inverting Differential Input (Gain = 1).
5
A+IN
Noninverting Differential Input (Gain = 1).
6
AMP-OUT-A
Single-Ended Amplifier Output (Gain = 2).
7
AMP-IN-A-1
Analog Input for A Side ADC (Nominally
0.5 V).
8
AMP-IN-A-2
Analog Input for A Side ADC (Nominally
1.0 V).
11
AV
EE
A
A Channel Analog Negative Supply Voltage (Nominally 5.0 V or 5.2 V).
12
AV
CC
A
A Channel Analog Positive Supply Voltage (Nominally 5.0 V).
14
ENCODEA
Complement of Encode; Differential Input.
15
ENCODEA
Encode Input; Conversion Initiated on Rising Edge.
17
DV
CC
A
A Channel Digital Positive Supply Voltage (Nominally 5.0 V/ 3.3 V).
18, 19, 37, 38
NC
No Connect.
2025, 2833
D0AD11A
Digital Outputs for ADC A. D0 (LSB).
26, 27
DGNDA
A Channel Digital Ground.
34
DROUTA
Data Ready A Output.
36
DROUTB
Data Ready B Output.
3942, 4552
D0BD11B
Digital Outputs for ADC B. D0 (LSB).
43, 44
DGNDB
B Channel Digital Ground.
53
DV
CC
B
B Channel Digital Positive Supply Voltage (Nominally 5.0 V/ 3.3 V).
54, 57, 60, 61, 67, 68
AGNDB
B Channel Analog Ground. A and B grounds should be connected as close to the
device as possible.
55
ENCODEB
Encode Input; Conversion Initiated on Rising Edge.
56
ENCODEB
Complement of Encode; Differential Input.
58
AV
CC
B
B Channel Analog Positive Supply Voltage (Nominally 5.0 V).
59
AV
EE
B
B Channel Analog Negative Supply Voltage (Nominally 5.0 V or 5.2 V).
62
AMP-IN-B-2
Analog Input for B Side ADC (Nominally
1.0 V).
63
AMP-IN-B-1
Analog Input for B Side ADC (Nominally
0.5 V).
64
AMP-OUT-B
Single-Ended Amplifier Output (Gain = 2).
65
B+IN
Noninverting Differential Input (Gain = 1).
66
BIN
Inverting Differential Input (Gain = 1).
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