reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
25 ns Instruction Cycle Time 40 MIPS Sustained
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Power-Down Mode Featuring Low CMOS Standby
ADSP-2100 Family Code Compatible, with Instruction
4K Words On-Chip Data Memory RAM
Powerful Program Sequencer Provides
16-Bit Internal DMA Port for High Speed Access to
Two Double-Buffered Serial Ports with Companding
Through Internal DMA Port
13 Programmable Flag Pins Provide Flexible System
ICE-PortTM Emulator Interface Supports Debugging
digital signal processing (DSP) and other high speed numeric
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
figured as 4K words (24-bit) of program RAM and 4K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equip-
ment. The ADSP-2184 is available in 100-lead LQFP package.
bit manipulations--bit set, bit clear, bit toggle, bit test-- ALU
constants, multiplication instruction (x squared), biased round-
ing, result free ALU operations, I/O memory transfers, and
global interrupt masking for increased flexibility.
process, the ADSP-2184 operates with a 25 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
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that is useful for single cycle context switching of the processor.
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle the ADSP-2184 can:
· Fetch the next instruction
· Perform one or two data moves
· Update one or two data address pointers
· Perform a computational operation
· Receive and transmit data through the two serial ports
· Receive or transmit data through the internal DMA port
· Receive or transmit data through the byte DMA port
· Decrement timer
of tools for software and hardware system development, sup-
ports the ADSP-2184. The System Builder provides a high level
method for defining the architecture of systems under develop-
ment. The Assembler has an algebraic syntax that is easy to
program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruction-
level simulation with a reconfigurable user interface to display
different portions of the hardware environment. A PROM
Splitter generates PROM programmer compatible files. The
C Compiler, based on the Free Software Foundation's GNU
C Compiler, generates ADSP-2184 assembly source code.
The source code debugger allows programs to be corrected in
the C environment. The Runtime Library includes over 100
ANSI-standard mathematical and DSP-specific functions.
development environment for the entire ADSP-21xx family: an
ADSP-218x based evaluation board with PC monitor software
plus Assembler, Linker, Simulator and PROM Splitter software.
The ADSP-21xx EZ-KIT Lite is a low cost, easy to use hardware
platform on which you can quickly get started with your DSP soft-
ware design. The EZ-KIT Lite includes the following features:
· Full 16-bit Stereo Audio I/O with AD1847 SoundPort
ging of an ADSP-2184 system. The emulator consists of hard-
ware, host computer resident software, and the target board
connector. The ADSP-2184 integrates on-chip emulation sup-
port with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection that requires fewer mechanical
clearance considerations than other ADSP-2100 Family EZ-
ICEs. The ADSP-2184 device need not be removed from the
target system when using the EZ-ICE, nor are any adapters
needed. Due to the small footprint of the EZ-ICE connector,
emulation can be supported in final board designs.
· Up to 20 breakpoints
· Single-step or full-speed operation
· Registers and memory values can be examined and altered
· PC upload and download functions
· Instruction-level emulation of program booting and execution
· Complete assembly and disassembly of instructions
· C source-level debugging
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections), as
well as the Target Board Connector for EZ-ICE Probe section
of this data sheet, for the exact specifications of the EZ-ICE
target board connector.
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User's Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Development
Tools Data Sheet.
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. The ADSP-2184 assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith-
metic shifts, normalization, denormalization and derive expo-
format control including multiword and block floating-point
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the output of any unit may be the input of any unit on the next
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-2184 executes looped code
with zero overhead; no explicit jump instructions are required to
simultaneous dual operand fetches from data memory and pro-
gram memory. Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four pos-
sible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
· Program Memory Data (PMD) Bus
· Data Memory Address (DMA) Bus
· Data Memory Data (DMD) Bus
· Result (R) Bus
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
ting the ADSP-2184 to fetch two operands in a single cycle, one
from program memory and one from data memory. The ADSP-
2184 can fetch an operand from program memory and the next
instruction in the same cycle.
Internal DMA port (IDMA port) for connection to external
systems. The IDMA port is made up of 16 data/address pins
and five control pins. The IDMA port provides transparent,
direct access to the DSPs on-chip program and data RAM.
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
slow memories and I/O memory-mapped peripherals with
programmable wait state generation. External devices can
gain control of external buses with bus request/grant signals
Normal execution mode requires the processor to halt while
buses are granted.
to six external interrupts (one edge-sensitive, two level-sensitive
and three configurable) and seven internal interrupts generated
by the timer, the serial ports (SPORTs), the Byte DMA port
and the power-down circuitry. There is also a master
serial interface with optional companding in hardware and a
modes of operation.
accept an external serial clock.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs, and three flags are
16-bit count register (TCOUNT) decrements every n processor
cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
ports (SPORT0 and SPORT1) for serial communications and
For additional information on Serial Ports, refer to the ADSP-
2100 Family User's Manual, Third Edition.
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
is generated after a data buffer transfer.
order to maintain maximum functionality and reduce package
size and pin count, some serial port, programmable flag, inter-
rupt and external bus pins have dual, multiplexed functionality.
The external bus pins are configured during RESET only, while
serial port pins are software configurable during program execu-
tion. Flag and interrupt functionality is retained concurrently
on multiplexed pins. In cases where pin functionality is re-
configurable, the default state is shown in plain text; alternate
functionality is shown in italics.
enable the corresponding interrupts, the DSP will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices or
set as a programmable flag.
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during RESET and cannot be changed while
the processor is running.
(8 MSBs Are Also Used as
Byte Memory Addresses)
BMS, CMS, PMS, DMS, and IOMS signals.
chip reset through the use of the Mode C pin. This pin is multi-
plexed with the DSP's PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are passive and active.
resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
programmable flag output without undue strain on the processor's
output driver. For minimum power consumption during
power-down, reconfigure PF2 to be an input, as the pull-up or
pull-down will hold the pin in a known state, and will not switch.
nal driver connected to the Mode C pin. A driver's output en-
able should be connected to the DSP's
ing full use of the PF2 pin as either an input or output.
the programmable flag as an output when connected to a three-
stated buffer. This ensures that the pin will be held at a constant
level and not oscillate should the three-state driver's level hover
around the logic switching point.
eleven possible interrupts and reset with minimum overhead.
The ADSP-2184 provides four dedicated external interrupt
IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six
external interrupts. The ADSP-2184 also supports internal
interrupts from the timer, the byte DMA port, the two serial
ports, software and the power-down control circuit. The inter-
rupt levels are internally prioritized and individually maskable
(except power-down and
IRQL0 and IRQL1 are level-sensitive and IRQE is edge-sensitive.
The priorities and vector addresses of all interrupts are shown in
interrupts taking precedence, or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.
ing and defines the
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
cally maintained during interrupt handling. The stacks are twelve
levels deep to allow interrupt, loop and subroutine nesting.
ing of the interrupts (including power-down), regardless of the
state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.
reduce the power dissipation when the device operates under
standby conditions. These modes are:
processor enter a very low power dormant state through hard-
ware or software control. Following is a brief list of power-down
features. Refer to the ADSP-2100 Family User's Manual, Third
Edition, "System Interface" chapter, for detailed information
about the power-down feature.
executing instructions in as few as 200 CLKIN cycles.
sor clock. The external clock can continue running during
power-down without affecting the lowest power rating and
200 CLKIN cycle recovery.
to save power (the processor automatically waits approxi-
mately 4096 CLKIN cycles for the crystal oscillator to start
or stabilize), and letting the oscillator run to allow 200 CLKIN
to be executed before optionally powering down. The power-
down interrupt also can be used as a nonmaskable, edge-
where it left off or start with a clean context when leaving the
has entered power-down.