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Datasheet: ADS7608A4A-55 (A-Data Technology)

Synchronous DRAM(4M X 8 Bit X 4 Banks)

 

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A-Data Technology
A-Data
ADS7608A4A
Synchronous DRAM
4M x 8 Bit x 4 Banks
General Description
The ADS7608A4A are four-bank Synchronous
DRAMs organized as 4,194,304 words x 8 bits x 4
banks.
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
Features
JEDEC standard LVTTL 3.3V power supply
MRS Cycle with address key programs
-CAS Latency (2 & 3)
-Burst Length (1,2,3,8,& full page)
-Burst Type (sequential & Interleave)
4 banks operation
All inputs are sampled at the positive edge of
the system clock
Burst Read single write operation
Auto & Self refresh
4096 refresh cycle
DQM for masking
Package:54-pins 400 mil TSOP-Type II
Ordering Information.
Part No.
Frequency
Interface
Package
ADS7608A4A-5 200Mhz LVTTL
400mil
54pin
TSOPII
ADS7608A4A-55 183Mhz LVTTL
400mil
54pin
TSOPII
ADS7608A4A-6 166Mhz LVTTL
400mil
54pin
TSOPII
ADS7608A4A-7 143Mhz LVTTL
400mil
54pin
TSOPII
ADS7608A4A-7.5 133Mhz
LVTTL 400mil
54pin
TSOPII
Pin Assignment
54
53
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
52
51
50
49
48
47
46
45
44
43
36
37
35
34
33
41
42
40
39
38
32
31
30
29
Vss
DQ7
Vss
Q
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
V
SS
NC/RFU
DQM
CK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
V
DD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
54-pin plastic TSOP II 400 mil
Rev 1 April, 2001
1
A-Data
ADS7608A4A
Pin Description
PIN NAME
FUNCTION
CK
System Clock
Active on the positive edge to sample all inputs.
CKE Clock
Enable
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Chip Select
Disables or Enables device operation by masking or enabling all input
except CK, CKE and L(U)DQM
A0~A11 Address
Row / Column address are multiplexed on the same pins.
Row address : RA0~RA11
Column address : CA0~CA9
BA0~BA1 Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ7 Data
Data inputs / outputs are multiplexed on the same pins.
L(U)DQM Data Mask
Makes data output Hi-Z,
/RAS
Row Address Strobe
Latches row addresses on the positive edge of the CLK with /RAS low
/CAS
Column Address Strobe
Latches Column addresses on the positive edge of the CLK with /CAS low
/WE
Write Enable
Enables write operation and row recharge.
VDD/VSS Power Supply/Ground
Power and Ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data Output Power/Ground Power supply for output buffers.
NC
No Connection
This pin is recommended to be left No Connection on the device.

Block Diagram
CK
CKE
Clock
Generator
Address
/CS
/RAS
/CAS
/WE
DQM
Mode
Register
Command Decoder
Control Logic
Row Decoder
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
Bank0
Bank2
Bank3
Bank1
Amplifier
Column Decoder
Data Control Circuit
Data Latch
DQ0~DQn
DQS
Rev 1 April, 2001
2
A-Data
ADS7608A4A

Absolute Maximum Ratings
Parameter Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
out
-1.0
~
4.6
V
Voltage on VDD supply relative to Vss
V
DD
, V
DDQ
-1.0
~
4.6
V
Storage temperature
T
STG
-55 ~ +150
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, T
A
= 0 to 70
Parameter Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
, V
DDQ
3.0 3.3 3.6
V
Input logic high voltage
V
IH
2.0 3.0
V
DD
+0.3 V
1
Input logic low voltage
V
IL
-0.3 0 0.8
V 2
Output logic high voltage
V
OH
2.4 -
- V
I
OH
=-2mA
Output logic low voltage
V
OL
- - 0.4
V
I
OL
=2mA
Input leakage current
I
IL
-5 - 5
uA
3
Output leakage current
I
OL
-5 - 5
uA
4
Note : 1. V
IH
(max)=4.6V AC for pulse width 10ns acceptable.
2.V
IL
(min)=-1.5V AC for pulse width 10ns acceptable.
3.Any
input
0V
V
IN
V
DD
+ 0.3V, all other pins are not under test = 0V.
4.Dout is disabled, 0V V
OUT
V
DD
.
AC Operating Condition
Voltage referenced to Vss = 0V, T
A
= 0 to 70
Parameter Symbol
Value
Unit
Note
AC input high / low level voltage
V
IH
/ V
IL
2.4 / 0.4
V
Input timing measurement reference level voltage
Vtrip
1.4
V
Input rise / fall time
TR / tF
1
Ns
Output timing measurement reference level
Voutfef
1.4
V
Output load capacitance for access time measurement
CL
50
pF
2
Note: 1. 3.15V V
DD
3.6V is applied for ADS7608A4A5.
2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details,
refer to AC/DC output load circuit.
Rev 1 April, 2001
3
A-Data
ADS7608A4A

Capacitance
TA=25, f-=1Mhz, VDD=3.3V
Parameter Pin
Symbol
Min
Max
Unit
CLK Cl1
2.5
4
pF
Input capacitance
A0~A11,BA0,BA1,CKE,/CS,/RAS,
/CAS,/WE,DQM
Cl2 2.5
5
pF
Data input / output capacitance DQM
CI/O
4
6.5
pF
Output load circuit
V
OH
(DC) = 2.4V,I
OH
= -2mA
V
OL
(DC) = 0.4V,I
OL
= 2mA
3.3 V
1200 ohms
870 ohms
50 pF
Output

DC Characteristics I
Parameter Symbol
Min
Max
Unit
Note
Input leakage current
I
LI
-1
1
uA
1
Output leakage current
I
LO
-1
1
uA
2
Output high voltage
V
OH
2.4
-
V
I
OH
= -4mA
Output low voltage
V
OL
-
0.4
V
I
OL
= 4mA
Note : 1.V
IN
= 0 TO 3.6V, All other pins are not tested under V
IN
= 0V.
2.D
OUT
is disabled, V
OUT
= 0 to 3.6.
Rev 1 April, 2001
4
A-Data
ADS7608A4A
DC Characteristics II
Speed
Parameter Symbol
Test
condition
-5
-5.5
-6
-7
-7.5
Unit Note
Operating Current
IDD1
Burst length=1, One bank active
tRCtRC(min),I
OL
=0mA
115
113
110
105 100 mA 1
IDD2P
CKEV
IL
(max), tCK=min
2
Precharge standby
current in power
down mode
IDD2PS CKEV
IL
(max), tCK=
2
mA
IDD2N
CKEV
IH
(min), /CSV
IH
(min),
tCK=min input signals are
changed one time during 2clks.
All other pins VDD-0.2V or
0.2V
15
Precharge standby
current in Non power
down mode
IDD2NS
CKEV
IH
(min), tCK=
Input signals are stable.
12
mA
IDD3P
CKEV
IL
(max), tCK=min
6
Active standby
current in power
down mode
IDD3PS CKEV
IL
(max), tCK=
5
mA
IDD3N
CKEV
IH
(min), /CSV
IH
(min),
tCK=min input signals are
changed one time during 2clks.
All other pins VDD-0.2V or
0.2V
30
Active standby
current in Non power
down mode
IDD3NS
CKEV
IH
(min), tCK=
Input signals are stable.
20
mA
Burst mode operating
current
IDD4
t
CK
t
CK
(min),I
OL
=0 mA
All banks active
160
160
155
150 150 mA 1
Auto refresh current IDD5
tRRCtRRC(min), All banks
active
160 mA
2
Self refresh current
IDD6
CKE0.2V
1 mA
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output
open.
2. Min. of tRRC is shown at AC characteristics.
Rev 1 April, 2001
5
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